UltraScale+ GTH IBIS-AMI Simulation for PCIe

[treuschel_bosch]

This question is related to the discussion at [1.]

A IBIS-AMI model of the GTH transceiver is available for download at [2]. Do I need to adapt these models in order to model PCIe operation across specific pins? If so, how can I do this? I am aware of IBISWriter [3], but I am not sure that this tool offers me a solution.

[1] https://forums.xilinx.com/t5/Serial-Transceivers/IBIS-Model-to-Simulate-PCIe-Lines/m-p/1061967
[2] https://www.xilinx.com/member/ultrascale_plus_ibis_ami.html
[3] https://www.xilinx.com/support/answers/50957.html

[jhua · Accepted solution]

The IBIS-AMI model is not dependent on pin location or package. You can use the same model.

In the simulation testbench setup, you will need to pay attention to the "simulation-specific parameters" described on page 16 of UG1183. Make sure the "setup recommendations" on page 17 are followed as well.

There is nothing you need specifically for PCIe, except that you will set the line rate to the targeted PCIe rate.

[treuschel_bosch]

Thank you for pointing out the "simulation-specific parameters" described on page 16 of UG1183. Depending on the simulation environment, is it equivalent to set them in the simulator GUI (if possible) or hard-code these in the .ami-file?

[jhua]

My recommendation is to set these in the simulation GUI. You can parameterize the AMI parameters of choice, then you can change them in the testbench as "variables".

I suggest to keep the AMI source files intact.