UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
419 Views
Registered: ‎01-07-2019

Ultrascale GTH Transceiver Dynamic Reconfiguration Reference Design

Hi, I am looking for Dynamic Reconfiguration Reference Design for Ultrascale GTH transceiver. I want to switch between two different data rates dynamically. Appreciate if anyone can share. Thanks.

0 Kudos
2 Replies
Moderator
Moderator
381 Views
Registered: ‎05-02-2017

Re: Ultrascale GTH Transceiver Dynamic Reconfiguration Reference Design

 

hi @hiralpatadiya,

 

unfortunately, there is no reference design , the customer has use the DRP ports in-order to achieve the  dynamic line switching 

 

The dynamic reconfiguration port (DRP) is an integral part of CMTs, clock management, XADC, serial transceivers, and the PCIe block.

The following are the interface requirements for the GT DRP interface.

Port Signal Definitions:

DCLK (Input)
The rising edge of this signal is the timing reference for all of the other port signals.

The required hold time for the other input signals relative to the rising edge of DCLK is zero (maximum).

Normally, DCLK is driven with a global clock buffer.

DEN (Input)
This signal enables all port operations.

If DWE is FALSE, it is a read operation, otherwise a write operation.

DEN should only be pulsed for one DCLK cycle.

DWE (Input)
When active, this signal enables a write operation to the port (see DEN).

DWE should only be pulsed for one DCLK cycle in GT DRP signal.

DADDR[m:0] (Input)
The value on this bus specifies the individual cell that is written or read on the next cycle of DCLK.

The address is presented in the cycle that DEN is active.

DI[n:0] (Input)
The value on this bus is the data that is written to the addressed cell.

The data is presented in the cycle that DEN and DWE are active, and is captured in a register at the end of that cycle, but the actual write occurs at an unspecified time before DRDY is returned.

DO[n:0] (Output)
If DWE was inactive when DEN was activated, the value on this bus when DRDY goes active is the data read from the addressed cell.

At all other times, the value on DO[n:0] is undefined.

The figures below show the timing relationships between the port signals for Write and Read operations.

Absolute timing parameters, such as maximum DCLK frequency, setup time, etc., are defined in the respective 7 series FPGAs data sheet.

timing016_201301110922583095.jpg



A monitor function has been added in attached GT primitives in order to capture multicycle access to DRP interface already in simulation.

 

Regards
Chandra sekhar
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if solution provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
297 Views
Registered: ‎01-07-2019

Re: Ultrascale GTH Transceiver Dynamic Reconfiguration Reference Design

Hi Chandra sekhar,

Thanks for prompt response. Would you please suggest me list of registers required to switch data rate between 5Gbps and 10Gbps?

Regards,

Hiral patadiya

0 Kudos