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Registered: ‎06-06-2018

Ultrascale+ GTY PRBS locked

Our design has an 64B/66B Aurora running over a GTY transceiver in a Zynq Ultrascale+ part.  I am trying to use the PRBS within the GTY to confirm the operation of the physical link between two interfaces and cannot gain access to the RXPRBSLOCKED port.  We have enabled the additional transceiver debug/status option in the Aurora IP configuration and this provides us with all of the PRBS signals (TX/RX PRBSSEL, etc.) but not this one.  Interestingly enough, if we enable this debug/status option on other transceiver with the PCIe interface, we do have access to this signal.

 

Any idea as to something specific to the Aurora interface that we need to do to see this port?

 

 

Dan B
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

回复: Ultrascale+ GTY PRBS locked

hi dburke@rockportnetworks.com

 

Aurora IP doesn't bring all PRBR ports to the top. 

I'm afraid you may need to manually edit the IP design files by text editors and pull the ports that you want to see to the top.

 

See below for the heirarchy.

 

Refer to page 109 (page 108 could also be helpful) of ug896 for the guideline to edit an IP source files.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug896-vivado-ip.pdf

 

Thanks,

Boris

 

 

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