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Visitor s941437
Visitor
670 Views
Registered: ‎06-08-2018

Ultrascale+ GTY RX CDR with frequency jitter

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Hi,

We have a receiver design on the UltraScale FPGA using the transceivers wizard to receive data from a sensor.

The line rate is 5.6Gb/s x 24 channels, and data is scrabmle (64b/66b), but we are not using the transceiver wizard to do the decoding.

CDR is locked after system power on and release from reset, but once the sensor starts processing (out of idle state), the CDR is not able to keep up with the lower frequency jitter. The result we are seeing is that when sensor is idle, the data received is correct, but it might sample at the wrong time after sensor is out of idle and more jitter is introduced to the line. We can acutally take a clock from the sensor and use that to sample the data, and the result will be correct, but through the GTY and CDR it is not.

We also did some analysis on the jitter. We found that the accumulated jitter, which casued a phase shift, on the data line is about +/-150ps over 500ns (2800 clock cycles). This is about 100fs per 178.5ps clock period.

Questions:

1. What is the jitter tolerance of the CDR? Can it recover the clock from +150ps to -150ps over 500ns?

2. Any configuration setting for the CDR we can tune? From the ug578 Ultrascale GTY user manual, there are very limited programable parameters.

3. We are using 8 Quads for the 24 channels, and RX refclk is set to take in from the MGTREFCLK0 (there are 6 coming into the FPGA to different Quads) and not from other Quad. This should be the cleanest way, correct?

4. The eye scan from the Vivado shows 0~40% open UI when sensor is not idle. However, this number does not seem to have correlation between how well the receiver gets the correct data. For example, one setup can gives me 10~40% on all channels but the receiver cannot rececive correct data. Another setup gives me 0% to 35% on all channels, but the receiver is able to get some correct data. Is there settings I need to adjust to correlate between the eye opening and the receiver sampling? Dwell BER is set to 1e-7

 

Thanks.

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Xilinx Employee
Xilinx Employee
635 Views
Registered: ‎11-29-2007

Re: Ultrascale+ GTY RX CDR with frequency jitter

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Hello,

I would suggest to make a closer analysis of the jitter in the sensor clock (i.e. a phase noise frequency domain measurement)

As a rough evaluation, thinking as that jitter as all sinusoidal (that is not true):

at 5.6Gbps the UI is 178.5ps. At 2 MHz (a period of 500ns) you are asking that the SJ tolerance is higher than 300/178=1,68UI and this is very close to the limit. It is likely that this jitter causes many errors in the recovered data.

We do not support manual configuration of the CDR. The supported configuration is the one provided by the Wizard.

Yes your REFCLK tree is clean.

You might try to help the CDR using the best possible equalizer setup. Please start from a new wizard setup and select the true channel IL. 

You might try to use as REFCLK the clock from the sensor (eventually clean it with a PLL with pass band higher than 2MHz).

The eye shape is important, but at the end you care about BER, not the eye amplitude. If a bit slip happens due to excessive jitter it is possible this will turn in a BER count but will not show up during the eye scan. If you set the Dwell to 1e-9 or lower you will help the eyescan to provide a more realistic eye, at the expense of the measurement time.

5 Replies
Xilinx Employee
Xilinx Employee
636 Views
Registered: ‎11-29-2007

Re: Ultrascale+ GTY RX CDR with frequency jitter

Jump to solution

Hello,

I would suggest to make a closer analysis of the jitter in the sensor clock (i.e. a phase noise frequency domain measurement)

As a rough evaluation, thinking as that jitter as all sinusoidal (that is not true):

at 5.6Gbps the UI is 178.5ps. At 2 MHz (a period of 500ns) you are asking that the SJ tolerance is higher than 300/178=1,68UI and this is very close to the limit. It is likely that this jitter causes many errors in the recovered data.

We do not support manual configuration of the CDR. The supported configuration is the one provided by the Wizard.

Yes your REFCLK tree is clean.

You might try to help the CDR using the best possible equalizer setup. Please start from a new wizard setup and select the true channel IL. 

You might try to use as REFCLK the clock from the sensor (eventually clean it with a PLL with pass band higher than 2MHz).

The eye shape is important, but at the end you care about BER, not the eye amplitude. If a bit slip happens due to excessive jitter it is possible this will turn in a BER count but will not show up during the eye scan. If you set the Dwell to 1e-9 or lower you will help the eyescan to provide a more realistic eye, at the expense of the measurement time.

Visitor s941437
Visitor
588 Views
Registered: ‎06-08-2018

Re: Ultrascale+ GTY RX CDR with frequency jitter

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Thanks,
Can you point me to the document that has the jitters tolerance spec?
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Xilinx Employee
Xilinx Employee
570 Views
Registered: ‎06-01-2017

Re: Ultrascale+ GTY RX CDR with frequency jitter

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You can find the JTOL at 80MHz in the datasheet DS923 Table 53. The full JTOL data would be in our characterization report, which you can download from here: https://www.xilinx.com/member/ultrascale_char_rpt.html (you will need to request for access).

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Visitor s941437
Visitor
558 Views
Registered: ‎06-08-2018

Re: Ultrascale+ GTY RX CDR with frequency jitter

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Hi,
I believe you are talking about the Rxppmtol parameter.
So in my case, the bit rate is <6.6Gb/s, meaning that Rxppmtol tolerance is +/-1250ppm.
For 5.6Gps bit rate, this gives me 0.4464ps tolerance (per UI?).
Does this mean that 178.57ps +/-0.2232ps is the maximum jitters tolerable per bit?
What about the limitation on integrator jitters over time? As mentioned in the original post that we have +/-150ps jitters over 500ns (2800 bits). In this case the per UI jitters is less than +/-1250ppm (300ps/2800UI=0.107ps), but according to gguasti, 300ps/178ps=1.68UI it is very close to the limit. Which document can I find this limit/spec?
Thanks.
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Xilinx Employee
Xilinx Employee
512 Views
Registered: ‎06-01-2017

Re: Ultrascale+ GTY RX CDR with frequency jitter

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Hi @s941437 

The RXPPMTOL is for the ppm difference between REFCLK and data.

In your case, for RX jitter tolerance, you should refer to the SJ jitter tolerance spec in the same table.

For 5Gbps and 6.6Gbps, the JTOL limit at 80MHz is 0.44UI. You are asking for 1.68UI at 2MHz.

For complete JTOL graph, please download the characterization report at:

https://www.xilinx.com/member/ultrascale_char_rpt.html (you will need to request for access).

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