cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Contributor
Contributor
176 Views
Registered: ‎05-07-2018

Ultrascale+ GTY and Fracxo

Hi,

I am using ZCU216 EVB(xczu49dr-ffvf1760-2-e-es1 part) and VIVADO 2019.2.1.

I want to make an example design of FRACXO IP with GTY transceiver. ( I using xapp1276 )

I downloaded the design files form the xapp1276 and ran it in Vivado but I was not able to make example design of FRACXO IP with GTY trans. (I have only GTY example design files)

I followed the instructions below:

It is strongly recommended to be familiar with the example design. Recommendation on constraints, clocking, resets, GT connections and settings must be respected.
Please refer to XAPP589, XAPP1241, XAPP1276 and XAPP1308 for operating instructions
1) Install Xilinx Vivado 2016.4 or later tools.
2) Add the IP repository to your project: Tools-->Project Options, select IP on the left pan, click "Add Repository" and select PICXO_FRACXO folder
In non project mode, the following commands can be used:
>>set_property ip_repo_paths <path to ip repository>/PICXO_FRACXO [current_fileset]
>>update_ip_catalog
3) In the IP catalog, select PICXO_FRACXO, right click-->Customize IP
In non project mode, the following command can be used:
>>create_ip -name PICXO_FRACXO -vendor xilinx.com -library ip -module_name ip_name
4) Right Click-->Generate Example design

 

Is there something I'm missing , how can I made a working example design of FRACXO IP with GTY transceiver?

 

Thanks!

Patolsky

0 Kudos
Reply
1 Reply
Moderator
Moderator
36 Views
Registered: ‎11-09-2015

HI @patolsky 

First note that XAPPs are usually tested (thus supported) in a single tool version. In the case of the xapp1276 this is 2019.1.

So if the project is not working or not building properly, I would highly recommend to go back to the version mentioned in the xapp.

With that said I think I have found the issue as I was able to make it build in 2020.2. The 2 following steps need to be done:

  • In the project settings, disable core container
    core.JPG
  • Make sure you generate the IP output products before generating the example design

Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply