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ppotapov
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Registered: ‎08-09-2018

Ultrascale Plus transceiver wizard not working on the hardware.

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Hello.

I have been poking around into the transceiver wizard recently. I have a KCU116 board. I had been working with this core for a while in simulation and simulation seems to work as expected. Recently I transitioned to testing my design on the board. I generated the example design for the core just to see if there are any problems with that. The example design fails to establish a link. With some poking the issue seems to have isolated to the pll lock. I exposed some extra ports as well. The clock_lost is set high on the device(The LOCKDETCLK has a clock source). I think I am missing something basic at this point. Any insights of what is possibly missing?

Here is the part of constraints file that I added aside from the false paths
provided by sample design:

set_property PACKAGE_PIN M2 [get_ports ch0_gtyrxp_in]
set_property PACKAGE_PIN C9 [get_ports link_down_latched_out]
set_property IOSTANDARD LVCMOS33 [get_ports link_down_latched_out]
set_property PACKAGE_PIN D9 [get_ports link_status_out]
set_property IOSTANDARD LVCMOS33 [get_ports link_status_out]
set_property PACKAGE_PIN A10 [get_ports link_down_latched_reset_in]
set_property PACKAGE_PIN A9 [get_ports hb_gtwiz_reset_all_in]
set_property IOSTANDARD LVCMOS33 [get_ports link_down_latched_reset_in]
set_property IOSTANDARD LVCMOS33 [get_ports hb_gtwiz_reset_all_in]

set_property PACKAGE_PIN P6 [get_ports mgtrefclk0_x0y2_n]
set_property PACKAGE_PIN P7 [get_ports mgtrefclk0_x0y2_p]

create_clock -period 6.400 -name clk_mgtrefclk0_x0y2_p [get_ports mgtrefclk0_x0y2_p]

set_property LOC GTYE4_CHANNEL_X0Y8 [get_cells -hierarchical -filter {NAME=~*gen_channel_container[2].*gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST}]

Physical ResourcesPhysical ResourcesBasic configBasic config

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eschidl
Xilinx Employee
Xilinx Employee
687 Views
Registered: ‎10-19-2011

Hi @ppotapov ,

you would probably either need to set the frequency for the SI5328 to 156.25MHz or switch to the MGTREFCLK1 of bank 226 which is driven from SI570.
The SI570 has the 156.25MHz as default.

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1 Reply
eschidl
Xilinx Employee
Xilinx Employee
688 Views
Registered: ‎10-19-2011

Hi @ppotapov ,

you would probably either need to set the frequency for the SI5328 to 156.25MHz or switch to the MGTREFCLK1 of bank 226 which is driven from SI570.
The SI570 has the 156.25MHz as default.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post