03-16-2021 11:37 PM
I am trying to understand the clocks naming scheme as referred to in the various documents. (GTH , RX related)
Figure 4-17 in UG576 lays out the optional clocks to forward to the TXOUTCLK port.
1. It seems that the RXOUTCLKPCS and RXOUTCLKPMA are connected. What are the differences between them?
2. Is the RXOUTCLKPCS is what usually called the RECOVERED CLOCK?
3. What is the relation between the inputs USRCLK and USRCLK2 to RXOUTCLKPCS and RXOUTCLKPMA?
4. What is the XCLK?
5. In the JESD204 PHY, I saw that: rxoutclksel = 3'H2 (=RXOUTCLKPMA). Is that mean that the rxoutclk output port is the recovered clock?
6. In the JESD204 PHY how can I enter to the rx_core_clk the clock from the cpll?
03-17-2021 09:41 AM
1. I generally think of them as the same but it is literally the clock that drives the PCS portion of the receiver and the clock that drive the analog (PMA) section of the receiver.
2. Any clock that comes after the phase interpolator is the recovered clock but potentially with a different amount of phase delay. If the CDRHOLD is applied, though, there is no recovered clock.
3. The RXUSRCLK is usually the RXOUTCLK, which could be the PCS or PMA clock, fed back to the GT such that it has a significant phase delay and can't be considered the same clock domain.
4. XCLK is one of the reciever's clock domains. See UG576 Figure 4-34 to see the domains.
5. Yes, unless CDR is held.
6. ? maybe ask the IP forum for specific instructions on that IP. You can get a version of the refclk through the muxes in the figure you showed or directly through the IBUF_GTE4s ODIV2 output. To get the CPLL clock you would have to set the CDRHOLD turning off the phase interpolator and choose the PCS or PMA clock output. If you turn off the phase interpolator, however, you won't have a recovered clock that you might need.