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Adventurer
Adventurer
737 Views
Registered: ‎09-03-2015

Unroutable gtrefclk connection from BUFG_GT

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Hello guy.

I am using the 10G Ethernet IP Core and the 1G Ethernet Sgmii IP from Xilinx for a Zynq Ultrascale device.

Both are using Tranceivers. For the 10G, we have an external differential clock input. For the 1G not.

My idea was, to connect the gt_refclk_out signal from the 10G IP to the gtreclk from the SGMII IP .

The SGMII IP is used with shared logic in example design. See picutre below:

block_design.PNG

After the Implementation, i see an unroutable behaivior.

In the schematic, i see that a BUFG_GT is used for the gt_refclk_out.

schematic.PNG

 

So what is wrong in this routing? Can't i connect a BUFG_GT to gtrefclk of a Tranceiver?

How can i solve this problem?

 

Thank you very much

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Xilinx Employee
Xilinx Employee
706 Views
Registered: ‎08-07-2007

回复: Unroutable gtrefclk connection from BUFG_GT

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hi @astei87 

 

gt_refclk_out seems connected to ODIV2 of IBUFDS_GTE4. ODIV2 cannot drive GTREFCLK.

we may have to figure out how to bring the IBUFDS_GTE4 out of the IP.

You can select Chared Logic in Example design and manually instantiate the IBUFDS_GTE4 and GT COMMON in the block design.

 

Thanks,

Boris

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

回复: Unroutable gtrefclk connection from BUFG_GT

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hi @astei87 

 

gt_refclk_out seems connected to ODIV2 of IBUFDS_GTE4. ODIV2 cannot drive GTREFCLK.

we may have to figure out how to bring the IBUFDS_GTE4 out of the IP.

You can select Chared Logic in Example design and manually instantiate the IBUFDS_GTE4 and GT COMMON in the block design.

 

Thanks,

Boris

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Adventurer
Adventurer
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Registered: ‎09-03-2015

回复: Unroutable gtrefclk connection from BUFG_GT

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thx borisq,

ok i instantiate the 10G IP with shared logic in example design. The i instantiate the IBUFDS_GTE4 and connect the output to

both (10G and 1G) IP's, right?

 

I have another question. We have already a differential input Clock also for the 1G Sgmii IP but it is to high. It is 625 Mhz.

The maximum clock i can select in the IP is the 312,5Mhz. Could i devide this clock and drive the GTREFCLK?

But the IBUFDS_GTE4/ODIV2 doesn't work you said. Is there another possibility?

 

Thanks very much.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

回复: Unroutable gtrefclk connection from BUFG_GT

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hi @astei87 

 

I think you can select "GT in Example Design".

you can use GT Wizard to generate GT, where 625Mhz is allowed for 1.25Gbps.

 

Thanks,

Boris

 

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Adventurer
Adventurer
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Registered: ‎09-03-2015

回复: Unroutable gtrefclk connection from BUFG_GT

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ok, but how can i use the SGMII IP then? Because there is already a GT included.
Can i somehow replace my GT Core with that one in the IP?

Thanks
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

回复: Unroutable gtrefclk connection from BUFG_GT

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hi @astei87 

 

if you select GT in Example Design, the SGMII IP doesn't include a GT.

 

Thanks,

Boris

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Adventurer
Adventurer
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Registered: ‎09-03-2015

回复: Unroutable gtrefclk connection from BUFG_GT

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ahh i see, i haven't noticed this Checkbox.
Thank you very much
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Adventurer
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Registered: ‎09-03-2015

回复: Unroutable gtrefclk connection from BUFG_GT

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one last question.

You have said, that i could instantiate my own GT and select 625Mhz.

Why is this configuration then not possible in the SGMII IP Core? There i can select till max 312.5Mhz.

It must be a special reason for that, isn't it?

 

Thank you

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

回复: Unroutable gtrefclk connection from BUFG_GT

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hi @astei87 

 

I guess the SGMII IP only tested with those ref clocks in the list.

 

Thanks,

Boris

 

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