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eml
Explorer
Explorer
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Registered: ‎03-31-2017

Unrouted nets on IBUFDS_GTE2

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So what exactly are the rules for an IBUFDS_GTE2 on Virtex-7?

I have a differential clock input on bank n, on MGTREFCLK0P/N. This drives a 10G PCS/PMA core on bank n+1, and an Aurora core on bank n-1 (the three banks are actually 117, 118, and 119).

Vivado eventually complains about a couple of unrouted nets on this clock, but it doesn't actually say what the problem is.

Presumably the problem is that Vivado doesn't realise that the IBUFDS components in the two cores are the same buffer and can be merged? Do I have to hack out the buffers and instantiate a single one externally? Or is there a more fundamental problem?

The Aurora core has an option to run from a single-ended refclk, which I haven't used, because it doesn't seem like a very good idea. Maybe this is related?

 

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roym
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Registered: ‎07-30-2007

You have to "hack" out the IBUFDS_GTE* buffers.  They are usually on the top level so this shouldn't be too big an issue but you can't instantiate three input buffers for one clock.




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roym
Moderator
Moderator
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Registered: ‎07-30-2007

You have to "hack" out the IBUFDS_GTE* buffers.  They are usually on the top level so this shouldn't be too big an issue but you can't instantiate three input buffers for one clock.




----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
Be sure to visit the Resources post periodically to keep up with the latest
https://forums.xilinx.com/t5/Serial-Transceivers/Serial-Transceiver-Forum-Guidelines-and-Useful-Resources/td-p/1173590
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eml
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Registered: ‎03-31-2017

Ok, thanks.

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