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Adventurer
Adventurer
196 Views
Registered: ‎03-21-2013

Using DRU clock for 2 HDMI RX ports

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Hello.

I'm using Zynq Ultrascale+ MPSoC.

Using IP Integrator I need to know how to connect the DRU refclk input to 2 HDMI RX quads.

The first quad is fine - the Video PHY mgtrefclk1 pins take the differential DRU refclk directly as an input.

However, I would like a second HDMI RX quad to use the same DRU refclk clock, fed from the first HDMI RX quad (via North/South clock paths I think). How do I achieve this? I can't use the recommended IBUFDS_GT -> BUFG_GT arrangement because I would need to drive a differential input signal to 2 places. Can I use one of the clock outputs from the first HDMI RX quad? How do I get the DIV2 clock?

 Thanks

 

Clive

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Adventurer
Adventurer
148 Views
Registered: ‎03-21-2013

Re: Using DRU clock for 2 HDMI RX ports

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I managed to fix this using Advanced Clocking Mode for the Video PHY at X0Y12. This removes the IBUGDS from the Video PHY and allows me to instantiate  them manually.  Quad X0Y12 now takes the single-ended version of the DRU clock (and its DIV2 version) as an input from an externally instantiated IBUFGDS. The external availability of the single-ended DRU clock allows me to route this signal to the other Video PHY. The only complication is that the Advanced Clocking Mode applies to the entire PHY – not just the DRU clock – it also removes the IBUFGDS from the other clock input (HDMI RX clk) on the X0Y12 PHY. To counter this, I simply instantiated an IBUFGDS for this clock.

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Moderator
Moderator
157 Views
Registered: ‎07-30-2007

Re: Using DRU clock for 2 HDMI RX ports

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If they are adjacent quads the output of the IBUFDS_GTE* can drive both of them.  You would need to make sure that the second quad isn't instantiating its own IBUFDS_GTE*.  The output of the IBUFDS_GTE* does not normally drive a BUFG_GT.  The O output directly drives the GT_CHANNEL or GT_COMMON.  It can drive a clock through a BUFG_GT and into the fabric but the GT_CHANNEL/COMMON routes are dedicated.

Roy


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Adventurer
Adventurer
149 Views
Registered: ‎03-21-2013

Re: Using DRU clock for 2 HDMI RX ports

Jump to solution

I managed to fix this using Advanced Clocking Mode for the Video PHY at X0Y12. This removes the IBUGDS from the Video PHY and allows me to instantiate  them manually.  Quad X0Y12 now takes the single-ended version of the DRU clock (and its DIV2 version) as an input from an externally instantiated IBUFGDS. The external availability of the single-ended DRU clock allows me to route this signal to the other Video PHY. The only complication is that the Advanced Clocking Mode applies to the entire PHY – not just the DRU clock – it also removes the IBUFGDS from the other clock input (HDMI RX clk) on the X0Y12 PHY. To counter this, I simply instantiated an IBUFGDS for this clock.

0 Kudos