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Explorer
Explorer
317 Views
Registered: ‎09-25-2017

Using RXOUTCLK as Tx MGTREFCLK

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Target FPGA : Zynq Ultrascale+

I would like to pass RXOUTCLK to an external clock cleaner, then use the output as MGTREFCLK for TX.  Rx is 12Gbps, Tx is 12Gbps.  The received data is processed and re-transmitted using the aforementioned MGT TX.

I have FIFOs in path to handle momentary jitter between RX data rate and TX data rate.

But I am concerned about long term clock slip between RX clk and cleaned TX clk, which will cause data loss.

My question is, will the cleaned clock be able to maintain the same frequency as RX clock?

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Xilinx Employee
Xilinx Employee
290 Views
Registered: ‎08-07-2007

回复: Using RXOUTCLK as Tx MGTREFCLK

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hi wtneo@leica 

 

is it CPRI slave design? or something else.

if the incoming data remain the same frequency, the recover clock will maintain, and thereby the cleaned clock will maintain.

we have some boards with jitter attenuator like SI5328. you can do some evaluation.

 

Thanks,

Boris

 

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Xilinx Employee
Xilinx Employee
291 Views
Registered: ‎08-07-2007

回复: Using RXOUTCLK as Tx MGTREFCLK

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hi wtneo@leica 

 

is it CPRI slave design? or something else.

if the incoming data remain the same frequency, the recover clock will maintain, and thereby the cleaned clock will maintain.

we have some boards with jitter attenuator like SI5328. you can do some evaluation.

 

Thanks,

Boris

 

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

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Explorer
Explorer
283 Views
Registered: ‎09-25-2017

回复: Using RXOUTCLK as Tx MGTREFCLK

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Hi Boris,

  It is not CPRI, but the RX link will be always connected and constant data rate.

Regards,

Neo

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