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Explorer
Explorer
319 Views
Registered: ‎09-25-2017

Using RXOUTCLK as reference for PLL Frequency synthesis

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I would like to connect GTX rxdata to a 4:1 OSERDES directly.  OSERDES requires a x1 clock and a x4 clock for 4:1 output.

Therefore I intend to input RXOUTCLK to a PLL, then generate x1 and x4 clock.  The x1 clock is also used as rxusrclk to read out data from GTX.

x1 and x4 clock need to be phase aligned for OSERDES operation.

Question:

  Does RXOUTCLK has high jitter due to clock recovery, such that PLL lock will fail?  If this scheme is not recommended, what is the recommened clock topology so that I can constantly stream out rxdata.  I am unable to apply back pressure as data is coming from GTX Rx.

Regards,

Neo

 

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Moderator
Moderator
289 Views
Registered: ‎07-30-2007

Re: Using RXOUTCLK as reference for PLL Frequency synthesis

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RXOUTCLK can drive a PLL.  Any Fabric clock will have too much jitter to drive a GT but it can drive all Fabric interfaces.  In the same way it drives the RXUSRCLK it can drive other things. If it is constrained correctly the timing software will take care of all FPGA interfaces.  I'm not sure about the phase delay of driving this clocking out of the chip.  You must be careful to consider that this clock is only reliable when the RXCDR is locked.  It is not a continuous clock.




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Moderator
Moderator
290 Views
Registered: ‎07-30-2007

Re: Using RXOUTCLK as reference for PLL Frequency synthesis

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RXOUTCLK can drive a PLL.  Any Fabric clock will have too much jitter to drive a GT but it can drive all Fabric interfaces.  In the same way it drives the RXUSRCLK it can drive other things. If it is constrained correctly the timing software will take care of all FPGA interfaces.  I'm not sure about the phase delay of driving this clocking out of the chip.  You must be careful to consider that this clock is only reliable when the RXCDR is locked.  It is not a continuous clock.




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