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Visitor ammarshaqeel
Visitor
187 Views
Registered: ‎08-06-2019

Using Transceiver for Source Synchronous Communication

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Hi Everyone

I'm a university student trying to complete a project using the GTY transciver on the VCU118 board.

At the moment I have set up the transciever example project, and I am trying to run the transciever as source synchronous system, by asserting RXCDRHOLD = 1’b1 and RXCDROVRDEN = 1’b0.

At the moment, once RXCDRHOLD has been asserted the link becomes unstable.

The idea is that by modifying the phase of the clock externally, I would be able to read the data without needing a QPLL.

If anyone had any experience with this or could point out any obvious flaws in this approach it would be much appreciated.

 

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Teacher drjohnsmith
Teacher
141 Views
Registered: ‎07-09-2009

Re: Using Transceiver for Source Synchronous Communication

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The question is raised

This must be a very interesting project that you dont want to use the built in QPLL designed for the job , can you elaborate on the work a little for us please ?

If you want to run nearer 1 Gb/s, the the SerDes on every IO pin of the FPGA might be a way forward .

example
https://www.xilinx.com/support/documentation/application_notes/xapp1274-native-high-speed-io-interfaces.pdf
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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5 Replies
Moderator
Moderator
156 Views
Registered: ‎07-30-2007

Re: Using Transceiver for Source Synchronous Communication

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GT's are used at frequencies where ordinary source synchronous techniques break down.  I'm not sure you can be successful with this.  When you set the cdr hold high you are turning off the mechanism that generates the recovered clock.  Your control of the refclk needs to make up for this loss.  It is completely expected that the link goes unstable if it is not run from a recovered clock. 




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Teacher drjohnsmith
Teacher
142 Views
Registered: ‎07-09-2009

Re: Using Transceiver for Source Synchronous Communication

Jump to solution
The question is raised

This must be a very interesting project that you dont want to use the built in QPLL designed for the job , can you elaborate on the work a little for us please ?

If you want to run nearer 1 Gb/s, the the SerDes on every IO pin of the FPGA might be a way forward .

example
https://www.xilinx.com/support/documentation/application_notes/xapp1274-native-high-speed-io-interfaces.pdf
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

Visitor ammarshaqeel
Visitor
78 Views
Registered: ‎08-06-2019

Re: Using Transceiver for Source Synchronous Communication

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The idea of the project is to try to demonstrate increased performance when switching between two different sources.
At the moment if we switch from one source to another, there is a QPLL locking time.

 

If we are sending large amounts of data this locking time is neglible, but if we are sending very small packets then this locking time can be significant.

At least that's the idea.

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Adventurer
Adventurer
74 Views
Registered: ‎07-16-2009

Re: Using Transceiver for Source Synchronous Communication

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Hi @ammarshaqeel ,

please correct me if I am wrong. But you are traying to connect two TX to one RX through some multiplexer and than have both TX run on the same clock, so when you switch, the RX does not loose the clock?

Thank you for the explanation,

Jan

Visitor ammarshaqeel
Visitor
71 Views
Registered: ‎08-06-2019

Re: Using Transceiver for Source Synchronous Communication

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Hi @lordgalloth 

The setup is as you say (two TX and one RX), but I want to have each TX running on a different clock.

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