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Registered: ‎10-17-2019

Using vivado to control the SFP+ module

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I saw lots of people on the internet using IP catlog in vivado to control the SFP transceiver. Is there anyone programing verilog code to control it? I have trid it. However, I met some problems when I set the Tx and Rx pins of SFP transceivers. It seems that this kind of pins can not be used as normal pins (for example, a led). The board that I use is KCU116. And the software which is vivado always shows some critical warning like this:

  • [Common 17-55] 'set_property' expects at least one object. ["D:/Final Year Project/rx_test/rx_test.srcs/constrs_1/new/rx_pins.xdc":8]
  • [Common 17-55] 'set_property' expects at least one object. ["D:/Final Year Project/rx_test/rx_test.srcs/constrs_1/new/rx_pins.xdc":9]
  • [Common 17-55] 'set_property' expects at least one object. ["D:/Final Year Project/rx_test/rx_test.srcs/constrs_1/new/rx_pins.xdc":8]
  • [Common 17-55] 'set_property' expects at least one object. ["D:/Final Year Project/rx_test/rx_test.srcs/constrs_1/new/rx_pins.xdc":9]
  • [Vivado 12-1411] Cannot set LOC property of ports, Site location (GTYE4_CHANNEL_X0Y8) is not valid for the shape with the following elements: tx_OBUF_inst tx ["D:/Final Year Project/rx_test/rx_test.srcs/constrs_1/new/rx_pins.xdc":10]
  • [Vivado 12-1411] Cannot set LOC property of ports, Could not find a valid bel for the shape with the following elements: rx_IBUF_inst/INBUF_INST rx rx_IBUF_inst/IBUFCTRL_INST ["D:/Final Year Project/rx_test/rx_test.srcs/constrs_1/new/rx_pins.xdc":14]
  • [Common 17-69] Command failed: 'tx' is not a valid site name. ["D:/Final Year Project/rx_test/rx_test.srcs/constrs_1/new/rx_pins.xdc":11]
  • [Common 17-69] Command failed: 'rx' is not a valid site name. ["D:/Final Year Project/rx_test/rx_test.srcs/constrs_1/new/rx_pins.xdc":16]

What I want to do is let the FPGA board detect a sequence that received from SFP port and once it successfully detect it, the FPGA board will send a 1 through the SFP port.

I will attach my code and constraints file, anybody please help me!

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Xilinx Employee
Xilinx Employee
390 Views
Registered: ‎08-13-2007

Re: Using vivado to control the SFP+ module

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The short answer is no... If the SFP+ is hooked up to MGT/GTY (or GTH, etc.) pins on the board (versus the general purpose SelectIO FPGA pins), you need to go through the GT to access these - you can't access these directly from the programmable logic fabric - keep in mind that these circuits were designed for very high speed (28Gbps+ in this case) interfaces - something way beyond what you could do in a generic behavioral RTL design.

You'll need to use the transceiver wizard example design or something else (e.g. 25G Ethernet PHY) that contains the GTY.

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Registered: ‎10-17-2019

Re: Using vivado to control the SFP+ module

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Here is the verilog code:

module rx_test(
input wire clk_p,
input wire clk_n,
input wire rx,
output reg tx_d,
output reg tx
);
wire clk;
reg clk_div;
reg [7:0] i=0;
reg [23:0] counter=0;
reg [99:0] s;
reg [99:0] s_reg;
IBUFGDS osc_clk(.O(clk), .I(clk_p), .IB(clk_n));
always@(posedge clk)
begin
if(counter<1000000)
begin
counter=counter+1;
clk_div=1;
end
else if(counter<2000000)
begin
clk_div=0;
counter=counter+1;
end
else
begin
counter=24'b0;
clk_div=1;
end
end

always@(posedge clk_div)
begin
s=100'b1111111111111111111111111111111111111111111111111100000000000000000000000000000000000000000000000000;
s_reg<={s_reg[98:0],rx};
if( ~(s_reg~^s)==100'b0)
begin
tx_d=1;
tx=1;
end
else
begin
tx_d=0;
tx=0;
end
end
endmodule

 

 

 

 

 

 

And the constraints file:

#clock
set_property PACKAGE_PIN K22 [get_ports {clk_p}]
set_property IOSTANDARD LVDS [get_ports {clk_p}]
create_clock -name clk -period 3.333 [get_ports {clk_p}]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
#io
set_property PACKAGE_PIN G10 [get_ports {led}]
set_property IOSTANDARD LVCMOS33 [get_ports {led}]
set_property PACKAGE_PIN N5 [get_ports {tx}]
set_property LOC tx [get_cells tx_OBUF_inst]
set_property PACKAGE_PIN AB14 [get_ports {tx_d}]
set_property IOSTANDARD LVCMOS33 [get_ports {tx_d}]
set_property PACKAGE_PIN K2 [get_ports {rx}]
set_property LOC rx [get_cells rx_IBUF_inst/INBUF_INST]
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: Using vivado to control the SFP+ module

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Hello duanxushi@gmail.com 

I think Vivado critical warnings are already very clear.

  • [Common 17-55] 'set_property' expects at least one object. ["D:/Final Year Project/rx_test/rx_test.srcs/constrs_1/new/rx_pins.xdc":8]
  • [Common 17-55] 'set_property' expects at least one object. ["D:/Final Year Project/rx_test/rx_test.srcs/constrs_1/new/rx_pins.xdc":9]
  • [Common 17-55] 'set_property' expects at least one object. ["D:/Final Year Project/rx_test/rx_test.srcs/constrs_1/new/rx_pins.xdc":8]
  • [Common 17-55] 'set_property' expects at least one object. ["D:/Final Year Project/rx_test/rx_test.srcs/constrs_1/new/rx_pins.xdc":9]

 

Your design does not have “led” port, hence Vivado gave your this critical warnings

 

  • [Vivado 12-1411] Cannot set LOC property of ports, Site location (GTYE4_CHANNEL_X0Y8) is not valid for the shape with the following elements: tx_OBUF_inst tx ["D:/Final Year Project/rx_test/rx_test.srcs/constrs_1/new/rx_pins.xdc":10]

 

N5 is a transceiver pin . You cannot connect logic fabric directly to this pin.

 

  • [Vivado 12-1411] Cannot set LOC property of ports, Could not find a valid bel for the shape with the following elements: rx_IBUF_inst/INBUF_INST rx rx_IBUF_inst/IBUFCTRL_INST ["D:/Final Year Project/rx_test/rx_test.srcs/constrs_1/new/rx_pins.xdc":14]

 

Same for this critical warning . K2 is a transceiver pin. You cannot connect logic fabric directly to this pin.

 

  • [Common 17-69] Command failed: 'tx' is not a valid site name. ["D:/Final Year Project/rx_test/rx_test.srcs/constrs_1/new/rx_pins.xdc":11]
  • [Common 17-69] Command failed: 'rx' is not a valid site name. ["D:/Final Year Project/rx_test/rx_test.srcs/constrs_1/new/rx_pins.xdc":16]

 

Please use input/output port name with 3 characters or more. “tx” or “rx” is too short.

 

Hope this helps.

Regards
Leo

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Xilinx Employee
Xilinx Employee
442 Views
Registered: ‎08-13-2007

Re: Using vivado to control the SFP+ module

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As stated above, the GT (GTY/GTH here - GTY on the SFP module on the KCU116's KU5) are not normal SelectIO accessible from the fabric - particularly the TX & RX diff pairs.

You need to go through the GT:

https://www.xilinx.com/support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf

Many users use the appropriate GT higher level protocol (40GE, Aurora, JESD204) but it sounds like you'll want the transceiver wizard IP here and its example design as a starting point which leverage the GTYE3_CHANNEL/GTYE3_COMMON primitive.

https://www.xilinx.com/products/intellectual-property/ultrascale_transceivers_wizard.html

In short, it is significantly more complicated than what you have right now...

Highlighted
398 Views
Registered: ‎10-17-2019

Re: Using vivado to control the SFP+ module

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Hi barriet,

Thanks for your reply. 

Is there any methods that I can use GTY pins without IP. I just want to use verilog code to control it. 

Besides, I can not find what I should added in my code or constraints file.

Could you please tell me where I can find it?

Highlighted
Xilinx Employee
Xilinx Employee
391 Views
Registered: ‎08-13-2007

Re: Using vivado to control the SFP+ module

Jump to solution

The short answer is no... If the SFP+ is hooked up to MGT/GTY (or GTH, etc.) pins on the board (versus the general purpose SelectIO FPGA pins), you need to go through the GT to access these - you can't access these directly from the programmable logic fabric - keep in mind that these circuits were designed for very high speed (28Gbps+ in this case) interfaces - something way beyond what you could do in a generic behavioral RTL design.

You'll need to use the transceiver wizard example design or something else (e.g. 25G Ethernet PHY) that contains the GTY.

View solution in original post

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Explorer
Explorer
212 Views
Registered: ‎08-14-2013

Re: Using vivado to control the SFP+ module

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If you just want to set the pin high or low, what you could do is instantiate a transceiver instance in raw mode, and then tie all of the TX data pins to the level you want to drive on the pin. But it is not possible to connect anything to the pin other than the corresponding transceiver instance, as the pin is physically wired directly to a transceiver site on the FPGA and nothing else.
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