Here is the verilog code:
module rx_test(
input wire clk_p,
input wire clk_n,
input wire rx,
output reg tx_d,
output reg tx
);
wire clk;
reg clk_div;
reg [7:0] i=0;
reg [23:0] counter=0;
reg [99:0] s;
reg [99:0] s_reg;
IBUFGDS osc_clk(.O(clk), .I(clk_p), .IB(clk_n));
always@(posedge clk)
begin
if(counter<1000000)
begin
counter=counter+1;
clk_div=1;
end
else if(counter<2000000)
begin
clk_div=0;
counter=counter+1;
end
else
begin
counter=24'b0;
clk_div=1;
end
end
always@(posedge clk_div)
begin
s=100'b1111111111111111111111111111111111111111111111111100000000000000000000000000000000000000000000000000;
s_reg<={s_reg[98:0],rx};
if( ~(s_reg~^s)==100'b0)
begin
tx_d=1;
tx=1;
end
else
begin
tx_d=0;
tx=0;
end
end
endmodule
And the constraints file:
#clock
set_property PACKAGE_PIN K22 [get_ports {clk_p}]
set_property IOSTANDARD LVDS [get_ports {clk_p}]
create_clock -name clk -period 3.333 [get_ports {clk_p}]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
#io
set_property PACKAGE_PIN G10 [get_ports {led}]
set_property IOSTANDARD LVCMOS33 [get_ports {led}]
set_property PACKAGE_PIN N5 [get_ports {tx}]
set_property LOC tx [get_cells tx_OBUF_inst]
set_property PACKAGE_PIN AB14 [get_ports {tx_d}]
set_property IOSTANDARD LVCMOS33 [get_ports {tx_d}]
set_property PACKAGE_PIN K2 [get_ports {rx}]
set_property LOC rx [get_cells rx_IBUF_inst/INBUF_INST]
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
