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Observer tmindenh1
Registered: ‎01-24-2019

VCU118 GTY Loopback


I am trying to make a GTY Tranciever Loopback to test eye diagrams over a bus between a Zynq Ultrascale Dev Board to a Vitrex Ultrascale+ (VCU118) Dev Board over the FMC bus at a speed >16Gbps. After fussing with Vivado for a while now (using IBUFDS and IBUFDS_GTE4 primatives) as well as the out-of-box VCU118 contraint file (rev 2.0), I have come to the conclusion that we must use the GTY Transciever Wizard to access the GT Pins on the banks we need. I have not used the IP before and am unsure how to impliment this IP to a design. The diagram on UG576 (Figure 1-1 pg 16) seems to be close to what we need. 

The input will be IBERT GT to produce data from the Zynq to Virtex. I have attached a diagram of the high level overview of the system, as well as my previous attempts to impliment the design. I am aware I am probably going about this all wrong, just looking for some advice or a solution.


Tom M.

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2 Replies
Registered: ‎07-30-2007

Re: VCU118 GTY Loopback

Use PG182 for instructions on how to use the transceiver wizard.  For what you show here you should be able to set up a fairly straightforward IBERT design to test that loopback path.

Don't forget to reply, kudo, and accept as solution

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Xilinx Employee
Xilinx Employee
Registered: ‎12-10-2009

Re: VCU118 GTY Loopback

It seems from your diagram that you would like to do a far-end PMA loopback on the VCU118 board but you could just run IBERT on the VCU118 as well.  They use compatible patterns.  The GTY's can be enabled via IBERT or the GT Wizard for loopback mode or you can have the IBERT in the Zynq device communicated directly with an IBERT core in the VCU118 board using GTY transceivers. 


Loopback mode described on starting on page 86 of the GTY user guide


GTH User Guide


GTH IBERT Product Guide


GTY IBERT Product Guide






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