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Visitor purtsjon
Visitor
466 Views
Registered: ‎05-16-2018

Virtex 6 GTXE1 DRP Register for TX Phase/Delay

Hi

For the 7 series FPGAs there are DRP registers available for TX phase/delay alignment configuration on GTXE2. Kintex7:

TXPH_CFG (0x64)
TXDLY_LCFG (0x9F)

Are there any similiar (undocumented?) registers on a Virtex 6 to control the TX phase/delay alignment during runtime like on Kintex7?
In UG366 I can't find any way...

Thanks for your support.
Regards,
Jonas

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Xilinx Employee
Xilinx Employee
445 Views
Registered: ‎08-07-2007

回复: Virtex 6 GTXE1 DRP Register for TX Phase/Delay

hi @purtsjon

 

Virtex-6 GTX is a little different than 7 series GTX with phase and delay alignment feature.

Some features in 7 series GTX may not be applicable with Virtex-6 GTX.

 

why do you need to change those attributes during runtime on Kintex-7? what do you need in the application?

 

Thanks,

Boris

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Visitor purtsjon
Visitor
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Registered: ‎05-16-2018

回复: Virtex 6 GTXE1 DRP Register for TX Phase/Delay

Hi @borisq

The top priority is to get a deterministic timing of the TX path in the transceiver.
On the Kintex7 the automatic alignment has been disabled and the phase interpolator between PCS und PMA controlled manually depending on the TX FIFO half-full flag. This was a recommendation by a Xilinx expert.
When the automatic alignment was used some slight phase changes were seen after a link is re-established...

Now, we like to get the system working on a Virtex6 too. But this would require that the phase/delay alignment behaves similar...
Could you give some details about the differences?

Thanks,
jonas

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