12-20-2018 05:58 AM
I am attempting to use 2 GTXs to send signals. I use the ipcore – gtwizard2.7 of ISE v14.7 to configure. I choose TX buffer bypass mode and operate as the sequence picture of UG 476 .
When I simulate in the modelsim, the TXDLYRESETDONE can assert after TXDLYRESET asserts. But TXPHINITDONE never asserts after TXPHINIT asserts.
I don’t know how to solve the problem.
12-20-2018 10:20 AM
A buffer bypass simulation might take a long time depending on the speedup settings. How long did you simulate? What frequency is your system clock and txusrclk?
Attach your *.xci file and we might be able to look into this more.
12-20-2018 07:19 PM
Thanks for your replay. I use ISE v14.7, gtwizard v2.7 instead of vivado. The configuration of the ip core is like that, I use GTX_X1Y24 and GTX_X1Y25. The line rate is 6.25GHz, the reference clock and system clocks are both 125MHz, TXUSRCLK is 156.25MHz.
I bypass the TX buffer and cancel the 8B/10B encoding and don’t choose RXcomma alignment, channel bonding and clock correction.
The sequence picture of UG 476 is shown as
This is the outcome of simulation，GT0_TXOUTCLK_OUT (master) is the clock of GT0_TXUSRCLK_IN and GT1_TXUSRCLK_IN(slave). GT0_TXPHDLYRESET_IN is 1’b0, GT0_TXPHALIGNEN_IN is 1’b1。
GT0_TXDLYSRESET_IN asserts after GT0_TXRESETDONE_OUT， GT0_TXDLYSRESETDONE_OUT asserts successfully in 454875ns。
The GT0_TXPHINITDONE_OUT don’t assert in 949566ns.
12-21-2018 01:08 AM
are you simulating with the example design or your own design?
example design can be a start point.