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Visitor shanqitui_1
Visitor
587 Views
Registered: ‎12-20-2018

Virtex-7 GTX Transceiver buffer bypass mode: TXPHINITDONE never asserts

I am attempting to use 2 GTXs to send signals. I use the ipcore – gtwizard2.7 of ISE v14.7 to configure. I choose TX buffer bypass mode and operate as the sequence picture of UG 476 .

When I simulate in the modelsim, the TXDLYRESETDONE can assert after TXDLYRESET asserts. But TXPHINITDONE never asserts after TXPHINIT asserts.

I don’t know how to solve the problem.

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5 Replies
Moderator
Moderator
553 Views
Registered: ‎07-30-2007

Re: Virtex-7 GTX Transceiver buffer bypass mode: TXPHINITDONE never asserts

A buffer bypass simulation might take a long time depending on the speedup settings.  How long did you simulate?  What frequency is your system clock and txusrclk?

Attach your *.xci file and we might be able to look into this more.




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Visitor shanqitui_1
Visitor
525 Views
Registered: ‎12-20-2018

Re: Virtex-7 GTX Transceiver buffer bypass mode: TXPHINITDONE never asserts

    Thanks for your replay. I use ISE v14.7, gtwizard v2.7 instead of vivado. The configuration of the ip core is like that, I use GTX_X1Y24 and GTX_X1Y25. The line rate is 6.25GHz, the reference clock and system clocks are both 125MHz, TXUSRCLK is 156.25MHz.

 
2.jpg

 

    I bypass the TX buffer and cancel the 8B/10B encoding and dont choose RXcomma alignment, channel bonding and clock correction.3.jpg

4.jpg

 

5.jpg

 

The sequence picture of UG 476 is shown as1.jpg

     This is the outcome of simulation,GT0_TXOUTCLK_OUT (master) is the clock of GT0_TXUSRCLK_IN and GT1_TXUSRCLK_IN(slave). GT0_TXPHDLYRESET_IN is 1’b0, GT0_TXPHALIGNEN_IN is 1’b1。6.jpg

 7.jpg

GT0_TXDLYSRESET_IN asserts after GT0_TXRESETDONE_OUT, GT0_TXDLYSRESETDONE_OUT asserts successfully in 454875ns。8.jpg

 The GT0_TXPHINITDONE_OUT dont assert in 949566ns.

9.jpg

 

 

 

 

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Xilinx Employee
Xilinx Employee
513 Views
Registered: ‎08-07-2007

回复: Virtex-7 GTX Transceiver buffer bypass mode: TXPHINITDONE never asserts

hi @shanqitui_1

 

are you simulating with the example design or your own design?

example design can be a start point.

 

Thanks,

Boris

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268 Views
Registered: ‎10-15-2018

回复: Virtex-7 GTX Transceiver buffer bypass mode: TXPHINITDONE never asserts

hi @shanqitui_1 

I am having the same issue: https://forums.xilinx.com/t5/Serial-Transceivers/GTP-Manual-Phase-alignment-TXPHINITDONE-never-asserts

Did you find a solution to this problem ?

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Moderator
Moderator
254 Views
Registered: ‎07-30-2007

回复: Virtex-7 GTX Transceiver buffer bypass mode: TXPHINITDONE never asserts

You are not looking deep enough into the simualtion.  The signals aren't passed to the top level.  Look at the GTX channel block signals and the signals at the manual alignment block of the example design.




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