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Visitor rileybaird
Visitor
678 Views
Registered: ‎08-08-2018

[Vivado 12-1411] Cannot set LOC property of ports, Instance u_ibert_gth_core

Please see: https://forums.xilinx.com/t5/Implementation/Why-quot-Vivado-12-1411-Cannot-set-LOC-property-of-ports-quot/m-p/858042/highlight/false#M20839

I am also looking for a solution to this exact problem. I am not even using the PCIE core, but simply the IBERT for GTH transceivers core, and it causes the same error.

[Vivado 12-1411] Cannot set LOC property of ports, Instance u_ibert_gth_core/inst/QUAD[0].u_q/CH[0].u_ch/u_gthe4_channel can not be placed in GTHE4_CHANNEL of site GTHE4_CHANNEL_X0Y15 because the bel is occupied by u_ibert_gth_core/inst/QUAD[0].u_q/CH[3].u_ch/u_gthe4_channel(port:). This could be caused by bel constraint conflict 

The default (read-only) ibert_ultrascale_gth_0.xdc file made with the IBERT core appears to set the location here:

set_property LOC GTHE4_CHANNEL_X0Y12 [get_cells QUAD[0].u_q/CH[0].u_ch/u_gthe4_channel]

But it is a read-only file so it is not changeable. Is this a fundamental mis-understanding of how the PCIE ports work with ultrascale?

I am trying to use my own ports here in my own .xdc file but these are what cause the conflict:

set_property PACKAGE_PIN P4 [get_ports gth_rxp_i]
set_property PACKAGE_PIN P3 [get_ports gth_rxn_i]
set_property PACKAGE_PIN N6 [get_ports gth_txp_o]
set_property PACKAGE_PIN N5 [get_ports gth_txn_o]

These port names match what the IBERT core requires for inputs and outputs, so I'm wondering what it expects me to do.

I tried the solution of setting the nets to blank ports (the solution provided in the question I linked) but it didn't work.

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6 Replies
Xilinx Employee
Xilinx Employee
661 Views
Registered: ‎05-08-2012

Re: [Vivado 12-1411] Cannot set LOC property of ports, Instance u_ibert_gth_core

Hi @rileybaird.

I would re-check the IP Customization for IBERT to see if you can select specific GT locations. Most IPs have this ability. Otherwise, you would need to unplace the constrained GT (set_property LOC {} [get_cells get_cells QUAD[0].u_q/CH[0].u_ch/u_gthe4_channel]) before setting the I/O LOC constraints. A placement shape has been created that contains the GT CHANNEL and connected I/Os. The constraint on the CHANNEL affects the I/Os.

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Visitor rileybaird
Visitor
650 Views
Registered: ‎08-08-2018

Re: [Vivado 12-1411] Cannot set LOC property of ports, Instance u_ibert_gth_core

Thank you for the reply. I have tried to customize where the IP puts the channels, but there is literally no option for selecting which RX / TX pairs it is supposed to route to. It defaults to the pins MGTHRXN0 / MGTHTXN0.

I even try doing "unplace" on those pins while in the Package Pins view of the synthesized design, but it won't let me re-place them in the proper channel, nor can I put anything at all in the proper channel by double clicking on the Ports field.

I also tried your solution of unplacing the cell first but it gives me an error of:

[Common 17-165] Too many positional options when parsing 'QUAD[0].u_q/CH[0].u_ch/u_gthe4_channel', please type 'get_cells -help' for usage info. 

But indeed it doesn't have any more specifics beyond .../u_gthe4_channel even in the .xdc file.

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Xilinx Employee
Xilinx Employee
637 Views
Registered: ‎05-08-2012

Re: [Vivado 12-1411] Cannot set LOC property of ports, Instance u_ibert_gth_core

Hi @rileybaird.

Could you upload the IBERT .xci for reference?


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Visitor rileybaird
Visitor
631 Views
Registered: ‎08-08-2018

Re: [Vivado 12-1411] Cannot set LOC property of ports, Instance u_ibert_gth_core

In what manner should I upload? It doesn't let me upload .xci files. I can email it to you.
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Xilinx Employee
Xilinx Employee
594 Views
Registered: ‎05-08-2012

Re: [Vivado 12-1411] Cannot set LOC property of ports, Instance u_ibert_gth_core

Hi @rileybaird

This looks to be a connectivity issue. The IP generates a Quad or 4 GT CHANNELs. Each has its own set of constraints. The top level only connects to one of these. The constraints also only constrain ports for one GT, which conflicts with the original constraints. Are you intending to lane swap or change the ordering of the GT connectivity within the Quad? My understanding is that this is not advised, and a spearate Transceivers post should be made for any possible negative implications.

However, there is a way to unset the GT constraints, and set them in a separate order. Below is an example:

#Resetting GT CHANNELs
set_property LOC {} [get_cells u_ibert_gth_core/inst/QUAD[0].u_q/CH[0].u_ch/u_gthe4_channel]
set_property LOC {} [get_cells u_ibert_gth_core/inst/QUAD[0].u_q/CH[1].u_ch/u_gthe4_channel]
set_property LOC {} [get_cells u_ibert_gth_core/inst/QUAD[0].u_q/CH[2].u_ch/u_gthe4_channel]
set_property LOC {} [get_cells u_ibert_gth_core/inst/QUAD[0].u_q/CH[3].u_ch/u_gthe4_channel]

#Setting New Constraints
set_property LOC GTHE4_CHANNEL_X0Y12 [get_cells u_ibert_gth_core/inst/QUAD[0].u_q/CH[0].u_ch/u_gthe4_channel]
set_property LOC GTHE4_CHANNEL_X0Y13 [get_cells u_ibert_gth_core/inst/QUAD[0].u_q/CH[1].u_ch/u_gthe4_channel]
set_property LOC GTHE4_CHANNEL_X0Y14 [get_cells u_ibert_gth_core/inst/QUAD[0].u_q/CH[2].u_ch/u_gthe4_channel]
set_property LOC GTHE4_CHANNEL_X0Y15 [get_cells u_ibert_gth_core/inst/QUAD[0].u_q/CH[3].u_ch/u_gthe4_channel]

The images show the IP Customization GUI which allows a specific Quad to be selected and the single top-level port connecting to one out of four GTs.


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selection.png
connections_2.png
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Visitor rileybaird
Visitor
580 Views
Registered: ‎08-08-2018

Re: [Vivado 12-1411] Cannot set LOC property of ports, Instance u_ibert_gth_core

I have a ZCU104 board. It only has PCIE enabled on it's X0Y15 pins due to the FMC connector (226: P3, P4, N5, N6), as well as only having one channel enabled. We want to use the IBERT IP to test the routing of the PCIE on our board we have design to connect through the FMC connector.

I am attaching an image of what the IBERT core places as default pin placement. This is without me specifying anything in my own XDC and letting the core do the pin assignment. As you can see, it default uses X0Y12 instead of X0Y15. Just so other people can see what I'm talking about, here are the top level ports.package_pins.PNG

In terms of lane swapping or changing the order, we are not trying to do that. We are trying to simply utilize the lane we were given to use for this test. Can we do the test with the board we have? 

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