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Visitor
Visitor
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Registered: ‎06-26-2018

Vivado Transciever Wizard not showing 16-bit datapath for VU9P

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Looking at AR#69011, the latency of a 16-bit datapath is about half that of a 32-bit datapath for GTY transcievers. However, when I open the transciever wizard (both for Vivado 2018.3 and 2019.1), there is no option for a 16-bit datapath. Is this not supported?
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Teacher
Teacher
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Registered: ‎07-09-2009

its a question of how fast the fpga can get data into / out of the GTY.

 

If you have a line rate of say 10 Gb/s , then the clock rate for a 16 bit interface is to much for the FPGA,

      so the minimum is a 32 bit user interface.

 

If you were to drop the GTY line rate down to say 3 Gb/s , then you have the option of a 16 bit interface.

 

Please give Kudos if this was useful and close if it aswers your question.

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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Teacher
Teacher
394 Views
Registered: ‎07-09-2009

its a question of how fast the fpga can get data into / out of the GTY.

 

If you have a line rate of say 10 Gb/s , then the clock rate for a 16 bit interface is to much for the FPGA,

      so the minimum is a 32 bit user interface.

 

If you were to drop the GTY line rate down to say 3 Gb/s , then you have the option of a 16 bit interface.

 

Please give Kudos if this was useful and close if it aswers your question.

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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Visitor
Visitor
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Registered: ‎06-26-2018
Makes sense. Just curious-- is there a document that shows the maximum line rate for the different widths?
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Teacher
Teacher
385 Views
Registered: ‎07-09-2009

Sorry , dont know of said doc, Im certain its 'just' an equation,

but I'm lazy,

   I just tend to run the tool, it does all the nice calculatoins !!

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Xilinx Employee
Xilinx Employee
375 Views
Registered: ‎10-19-2011

Hi @cgonzo ,

have a look at the datasheet for the maximum user clock frequency for the transceiver. It is listed for the different data width. Then multiply the two.

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