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Participant
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Registered: ‎02-08-2019

Vx1 with GTX

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Hello 

We are planning to use zynq ultrascale  XCZU5CG-1FBVB900E4659 in our new design. This contains 16 GTX. We have following query.

1. Can we implement Vx1 protocol in its PL section?  Becase we colunt find Vx1 option in portocol section in its tranreceiver wixzard.

 

Thanks

Manish  

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: Vx1 with GTX

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Hello Manish @manb 

If your question is answered or your issue is solved, please kindly mark the most helpful response as solution (click on "Accept as solution" button below the reply).
So others can learn from your experience.

Thanks and Regards,
Leo

View solution in original post

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: Vx1 with GTX

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Hello Manish @manb 

1. XCZU5 is UltraScale+ MPSoC device.
    This device has 16 GTH ( no GTX available in US+ devices)

2. Regarding protocol support.
    What do you mean with Vx1 protocol ? Is it V-by-One HS from Thine Electronics (https://www.thine.co.jp/en/) ??

If this is the case then it is not supported.
Please read DS925 for GTH supported protocol (https://www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf), we do not have V-by-One in the list ?


Thanks & regards
Leo

XF_GTH_protocol_support.png
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Mentor
Mentor
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Registered: ‎06-16-2013

Re: Vx1 with GTX

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Hi @manb 

 

What kind of V-by-One do you implement ? V-by-One HS ?

Also, how much SS do you want to use ?

 

It depends on your target.

 

Best regards,

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Registered: ‎02-08-2019

Re: Vx1 with GTX

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Hello Leo,

Thanks for you feedback.

Yes you are right that his device has 16 GTH.

But I am surprise why Vby1 is not supported by GTH Transreceiver. I have checked Vby1 at GTP on Artix7 XC7A75T-1FGG676C. And GTP  have less speed then GTH.

Can you pls let us know about following 

1. Is GTH only support those protocl which is available on its list? 

2. Why Vby1 is not supported by GTH?

Thanks

Manish 

Manish

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: Vx1 with GTX

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Hello Manish @manb 

Yes this list is the official supported protocol for GTH.

GTP does support V-by-One (2.97/3.7125/1.485), you should be able to select V-by-one protocol from the GTP transceiver GUI preset. (Note that SSC is not supported)
I do not think we have characterize GTH transceive for V-by-One protocol. V-by-One has very strict SSC and frequency offset spec requirement I believe, which make this protocol not offially supported.


Thanks & regards
Leo

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Registered: ‎02-08-2019

Re: Vx1 with GTX

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Hello Leo 

Thanks for your prompt response.

pls clarify following 

 

1.  Is SSC means spread spectrum ?

2. Is Vby1 is not support on any of  ZYNQ/ZYNQ ultrascale architecturer?

waiting for your feedback.

Thanks

Mansih 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: Vx1 with GTX

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Hello Manish


1. Is SSC means spread spectrum ?

Yes.

2. Is Vby1 is not support on any of ZYNQ/ZYNQ ultrascale architecturer?

Yes. Xilinx do not officially support V-by-One spec with US/US+ transceivers.
You can double check on the data sheet of each device.

Thanks
Leo

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: Vx1 with GTX

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Hello Manish @manb 

If your question is answered or your issue is solved, please kindly mark the most helpful response as solution (click on "Accept as solution" button below the reply).
So others can learn from your experience.

Thanks and Regards,
Leo

View solution in original post

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Participant
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Registered: ‎02-08-2019

Re: Vx1 with GTX

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Hello Leo,

vx1.jpg

 

 

 

 

 

I am trying to implement Vx1 receiver core on Artix 7   Xc7a75tfgg676-1. 

In 7 series transreceiver wizard I found Vby1 no SSC option with reference clock 148.5 MHz refer attched snap shot.

I have following query

1.  Is Reference clock means that pixel clock of Received data will always 148.5MHz ? What is the significanc of reference clock because I couldnt find referene clock in Vx1 specification.

 

2. The Line rate is 2.97Gbps means that per lane speed is 2.97 Gbps.

Pls let us know that is my understand is correct.

Thanks

Manish 

vx1.jpg

 

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: Vx1 with GTX

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Hello @manb 

 

>Is Reference clock means that pixel clock of Received data will always 148.5MHz ?


No Referece clock and Pixel clock is different.

 

>What is the significanc of reference clock because I couldnt find referene clock in Vx1 specification.

Reference clock is the base clock for your GTX/GTP transceiver.
It is not part of V-by-One.
Please note that GTX/GTP has a stricg REFCLK phase noise requirement.
https://www.xilinx.com/support/answers/44549.html

>2. The Line rate is 2.97Gbps means that per lane speed is 2.97 Gbps.

Yes. Your understanding is correct.

 

Thank
Leo

 

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Registered: ‎02-08-2019

Re: Vx1 with GTX

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Hello Leo

Thanks for your prompt feedback.

I am receiving clock from CDR of GTP  in Vby1 receiver Core. Can I use this clock for my rest of FPGA components?

Is this clock is having jitter?

Thanks

Manish 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: Vx1 with GTX

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Hello @manb 

Yes, You can use recovered clock for internal/fabric logic. (see also UG476)
The recovered clock jitter performance will depends on stability of your serial input signal.

If the serial input is not stable, CDR will failed and you probably will see a lot of 8B10B disparity error or/and not-in-table error.

Thanks
Leo

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Re: Vx1 with GTX

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Hello Leo,

 

Thanks for your feedback. 

As I am new with GTP implementation, Just one question for regarding  Vx1 Receiver core with GTP implementation.

1. We are getting differential signal from Vx1 transmitter from outside world. How we can simulate this kind of senarior with GTP for Rx? I mean how we can provide differential input to GTP in simulation?

 

Thanks

Manish 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: Vx1 with GTX

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Hello Manish

I don't have a quick answer for your question above.
Maybe "Simulation and Verification" board can give you a better guidance on this query.
https://forums.xilinx.com/t5/Simulation-and-Verification/bd-p/SIMANDVERIBD

It would be great if your V-by-One Transmitter IP provider can give you sample of V-by-One serial input pattern , so you can save those data in a text file, and read the text file using fscanf function in the testbench, so you don't have to create the stimulus file yourself.

> Anything to add ? @roym  ,  @borisq 

Regards
Leo

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Registered: ‎02-08-2019

Re: Vx1 with GTX

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Hello Leo,

We configuring GTP transmitter wizard. We have created component and found following signal in  instantiate templete .

gt0_txusrclk_out : out STD_LOGIC;
 gt0_txusrclk2_out : out STD_LOGIC;

Are these reallly output signal because in GTP user guide I found these are input signals.

Pls let us know that why these signals are declared as output in instantiate templete by GTP transmitter wizard?

 

Thanks

Manish 

 

 

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Moderator
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Registered: ‎07-30-2007

Re: Vx1 with GTX

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R/TXUSERCLK signals are inputs on the GTPE2_CHANNEL, however,  these signals are the buffered R/TXOUTCLK buffered so if you are looking at the clocking module where the buffers reside then they would be outputs on their way to the GTPE2_CHANNEL block.   See page 78. UG482.  In addition, if you can generate the expected input stream from the VX1, in some manner, either RTL or from an input file you can simulate it. 




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Participant
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Re: Vx1 with GTX

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Hello

From User Guide I have following understanding 

1. TXUSERCLK/TXUSERCLK2  is input to GTP GTPE2_CHANNEL block

2. TXOUTCLK can be use to  drive TXUSRCLK and TXUSRCLK2  by MMCMs or PLLs,. (User Guide Page 78 to 81).

Pls let us know if my understanding is correct?

But still I coulnt understand that why following are declare as output by core generator tool if TXUSERCLK is always input to GTP.

gt0_txusrclk_out : out STD_LOGIC;
  gt0_txusrclk2_out : out STD_LOGIC;
  gt1_txusrclk_out : out STD_LOGIC;
  gt1_txusrclk2_out : out STD_LOGIC;
  gt2_txusrclk_out : out STD_LOGIC;
  gt2_txusrclk2_out : out STD_LOGIC;
  gt3_txusrclk_out : out STD_LOGIC;
  gt3_txusrclk2_out : out STD_LOGIC;

Thanks

Manish 

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Re: Vx1 with GTX

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Hello 

Thanks for your suggestion.

I have following query.

1.  I want to input the  RXUSRCLOCK  from clock  recovered from CDR circuit of GTP. I have set the RXUSRCLOCK source is RXOUTCLK. How can I ensure the RXOUTCLK is the clock from CDR circuit? Couldnt find any setting in Transreceiver Wizard to set the RXOUTCLK set to clock from CDR circuit.

2. What is the RXOUTCLK source by default?

Thanks

Manish 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: Vx1 with GTX

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Hello Manish @manb 

This is a new question. Could you please post a new question ? ( 1 post for 1 topic )

Answering your question:
Source for RXOUTCLK is selected using RXOUTCLKSEL parameter. (There is no default setting.)
grep the Transceiver RTL IP to find what is the setting for you IP.

See the following picture from the UG576/UG578.
RXOUTCLK.png

Thanks
Leo

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