What are "horizontal" and "vertical" opening in the .csv-file of the Eye Scan?

[friede]

Hello everyone!

In the .csv-file that contains the data of an Eye Scan there are the two values "vertical opening" and "horizontal opening". Can anybody explain how they are calculated or is there a definiton for them somewhere?
Can they be seen as rough values for the margin the system has at a certain BER?

Thanks
friede

[roym]

The opening is the numbers of steps (vertical)or percentage of the UI horizontal that sees no errors with the current number of samples.  It shows the margin that you have at the current number of samples taken.  It is usually used in conjunction with an "eye mask" to qualify a channel for production.  For instance, you might typically be looking for +-30 steps vertical clearance and +-.15 UI horizontal clearance at 10^9 samples to give a BER of 10^-15 over PVT.  (assuming you meet and continue meeting all the data sheet specs on voltage, noise etc.)

[simon]

Hi @friede 

A single eye scan measurement consists of accumulating the number of data samples (sample count) and the number of times that the offset sample disagreed with the data sample (error count).

The bit error ratio (BER) at the programmed vertical and horizontal offset is the ratio of the error count to the sample count. The sample count can range from tens of thousands to greater than 10^14. Which means the BER is lower if the vertical/horizontal offset is far away from the center. You can learn more from RX margin analysis, for BER calcucation, equation 4-2(LPM), equation 4-3(DFE) ug578:

https://www.xilinx.com/support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf

[friede]

Ok, thanks @roym & @simon for your answers!
It goes along with what I've read in the documents and the forum as well, but is there any description on how the IBERT automatically determines these specific values? I understand the whole process of the eye scan and it's architecture but at which location in the eye does the programm measure them? Is it the margin at horizontal and vertical zero?

@roym Another question besides this is how did you guys determine the values for horizontal and vertical clearance (the +-30 steps vertical and +-.15 UI horizontal at 10^9 samples).
I've read them in some other forum posts and I'm just curious. I guess they are just the result of Xilinx's experience with the behaviour of the transceivers and some tests right?

@simon I've already found these equations. Are they also valid for the UltraScale+ GTH Transceiver, because they can't be found in UG576? I would assume yes, because both transceivers are pretty similar to each other, but I just want to have that confirmed.

Thanks
friede

[roym]

Yes the margin needed across PVT is found through extensive temperature testing of worst and best case silicon.