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jg_bds
Scholar
Scholar
655 Views
Registered: ‎02-01-2013

What is the bias voltage for PS_MGTREFCLK inputs?

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We're measuring some PS_MGTREFCLKs (to a PS GTR, not a PL GTH) that we're providing to a ZU15EG.

2019-02-28_15-48-10.jpg

We're expecting the load-side of the AC-coupling caps to have a bias comparable to this:

2019-02-28_15-42-22.jpg

But what we're seeing is this:

GTR_REFCLK.png

The upper waveform is one leg of the 100-MHz LVDS reference clock on the source-side of the AC-coupling caps. It's biased ~1.3V. The lower waveform is the same leg on the load-side of the cap--and it's only biased at ~50 mV.

Is this normal?

-Joe G.

 

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borisq
Xilinx Employee
Xilinx Employee
609 Views
Registered: ‎08-07-2007

hi  @jg_bds 

 

Yes, it is expected.

GTR refclk is different than PL GTs.

It is terminated to 0V.

Please look at UG583 Figure 4-5 on page 185

http://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf

 

Thanks,

Boris

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borisq
Xilinx Employee
Xilinx Employee
610 Views
Registered: ‎08-07-2007

hi  @jg_bds 

 

Yes, it is expected.

GTR refclk is different than PL GTs.

It is terminated to 0V.

Please look at UG583 Figure 4-5 on page 185

http://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf

 

Thanks,

Boris

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