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jerry
Explorer
Explorer
314 Views
Registered: ‎04-16-2018

Which clock used to recovery data in GTP ?

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UG476 states "The GTP transceiver includes an RX elastic buffer to resolve differences between the XCLK and RXUSRCLK domains."
XCLK is the recovery clock in PMA, does it use XCLK to recovery data ? or use RXUSRCLK to recovery data ?

 

By the way, I'm not able to find the port "rxoutclksel" in the configuration gearbox, I only found "RXSYSCLKSEL"

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karnanl
Xilinx Employee
Xilinx Employee
224 Views
Registered: ‎03-30-2016

Hello @jerry 


UG476 is for 7-series GTX/GTH.
If you are using 7-series GTP, please see UG482 instead. ( https://www.xilinx.com/support/documentation/user_guides/ug482_7Series_GTP_Transceivers.pdf  )
Please see UG482 Table 2-6 for RXSYSCLKSEL explanation. This port used to select PLL clk source to drive RX datapath.

RXSYSCLKSEL.png

I believe RXOUTCLKSEL is set as a fixed value inside GTP core, by default RXOUTCLKPMA is selected.
RXOUTCLKSEL.png

RXOUTCLK_default.png

Kind regards
Leo


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karnanl
Xilinx Employee
Xilinx Employee
225 Views
Registered: ‎03-30-2016

Hello @jerry 


UG476 is for 7-series GTX/GTH.
If you are using 7-series GTP, please see UG482 instead. ( https://www.xilinx.com/support/documentation/user_guides/ug482_7Series_GTP_Transceivers.pdf  )
Please see UG482 Table 2-6 for RXSYSCLKSEL explanation. This port used to select PLL clk source to drive RX datapath.

RXSYSCLKSEL.png

I believe RXOUTCLKSEL is set as a fixed value inside GTP core, by default RXOUTCLKPMA is selected.
RXOUTCLKSEL.png

RXOUTCLK_default.png

Kind regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

View solution in original post