06-12-2018 06:05 AM
I'm trying to generate a IBERT ip example design for testing line rate at 28.125Gbps.
According to UG578 page 29:
"For UltraScale+ FPGAs, channels operating from 16.375 Gb/s up to 28.21 Gb/s can source a
reference clock from up to one Quad above and below. The Quad that is providing the
shared reference clock has the flexibility to use one of the dedicated reference clock input
pin pairs in that Quad. For line rates higher than 28.21 Gb/s, no reference clock sharing is
allowed, QPLL0 must use GTREFCLK00, and QPLL1 must use GTREFCLK01."
My data rate is under 28.21Gbps i.e i can share ref clock from up/down quad.
I want to share qpll0(refclk0_bank120) ref clock to upper quad and qpll1(refclk1_bank120) ref clock to lower quad . Qpll selection is available till 26Gbps.
Attached ip screenshot.
Am I missing something?
Thank-You in advance.