cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Adventurer
Adventurer
908 Views
Registered: ‎06-27-2016

Why only qpll0 is allowed in ibert ip for virtex Ultrascale+ at 28.125Gbps?

Jump to solution

Hi,

I'm trying to generate a IBERT ip example design for testing line rate at 28.125Gbps.

According to UG578 page 29:

   "For UltraScale+ FPGAs, channels operating from 16.375 Gb/s up to 28.21 Gb/s can source a
   reference clock from up to one Quad above and below. The Quad that is providing the
   shared reference clock has the flexibility to use one of the dedicated reference clock input
    pin pairs in that Quad. For line rates higher than 28.21 Gb/s, no reference clock sharing is
    allowed, QPLL0 must use GTREFCLK00, and QPLL1 must use GTREFCLK01."

<ug578>

 

 

My data rate is under 28.21Gbps i.e i can share ref clock from up/down quad. 

 I want to share qpll0(refclk0_bank120) ref clock to  upper quad and qpll1(refclk1_bank120) ref clock to lower quad . Qpll selection is available till 26Gbps.

Attached ip screenshot.

 

Am I missing something? 

Thank-You in advance.

 

 

ibert_28.jpg
0 Kudos
Reply
1 Solution

Accepted Solutions
Adventurer
Adventurer
1,079 Views
Registered: ‎06-27-2016

Found the answer in "DC and AC Switching Characteristics" of qplls.

These have different ranges 

"acdc"

View solution in original post

qpll_max_freq.png
1 Reply
Adventurer
Adventurer
1,080 Views
Registered: ‎06-27-2016

Found the answer in "DC and AC Switching Characteristics" of qplls.

These have different ranges 

"acdc"

View solution in original post

qpll_max_freq.png