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Explorer
Explorer
1,385 Views
Registered: ‎03-27-2017

XAPP1295 Error

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Target: VCU118

 

I am following the instructions given in XAPP1295 to insert the debug logic into my .dcp.

 

When I enter the command: insert_gt_dbg analyze <.dcp file> the following is the output in the TCL console:

 

INFO: [Project 1-604] Checkpoint was created with Vivado v2017.2.1 (64-bit) build 1957588
open_checkpoint: Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 9617.531 ; gain = 0.000 ; free physical = 110307 ; free virtual = 120984
Step 1 - checking design for GT and BUFG instances and prepare insert_gt_dbg.do
checking clock network ... INFO: [Timing 38-35] Done setting XDC timing constraints.
report_clock_networks: Time (s): cpu = 00:00:58 ; elapsed = 00:00:15 . Memory (MB): peak = 9931.262 ; gain = 313.730 ; free physical = 109758 ; free virtual = 120435
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {IS_PRIMITIVE==1 && LIB_CELL=~"*BUFG*" && LIB_CELL!~"*SYNC*"}'.
can't read "::_igd_clk_d": no such variable

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Xilinx Employee
Xilinx Employee
1,779 Views
Registered: ‎11-29-2007

please can you open the synthesized design and then manually generate the .dcp? I am concerned that in the dcp you are using something is missing.

-GG

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Xilinx Employee
Xilinx Employee
1,365 Views
Registered: ‎11-29-2007

hello,

how have you created the .dcp file? have you opened the synthesized design and then saved the .dcp?

is it a complete example design?

thanks

Giovanni

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Explorer
Explorer
1,361 Views
Registered: ‎03-27-2017

@gguasti The .dcp was created automatically when I synthesized my design. I copied this file for use in the instructions given in XAPP1295. This design is a complete user design which includes a GTY quad which I'd like to debug with the interface.

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Xilinx Employee
Xilinx Employee
1,780 Views
Registered: ‎11-29-2007

please can you open the synthesized design and then manually generate the .dcp? I am concerned that in the dcp you are using something is missing.

-GG

View solution in original post