04-28-2020 03:00 PM - edited 04-29-2020 12:35 AM
I use a GTH RX using QPLL0 with user datawidth at 64 bits in *RAW* mode ie no 8b/10n and no 64b/66b and no gearbox !
The datas send show that there is no inserted datas.
And the generated Rxusrclk2 has a ratio with the input ref clock of 64/66 (clkref : 187.5 Mhz => RxUsrClk2 : 181.82Mhz)
where is the problem ?
04-29-2020 05:03 AM
Hello @vt3
I generated a Transceiver Example Design with Vivado 2018.3.1 and 2019.2. (with configuration from screenshot above. You did not attach your xci file)
Unfortunately, I cannot reproduce your report.
Transceiver wizard generated RXUSRCLK/RXUSRCLK2 with expected clock period.
RXUSRCLK = 12000/32 = 375 MHz
RXUSRCLK2 = 12000/64 = 187.5 MHz
These are expected clock frequencies.
A few questions for you:
1. Did you see these behavior on simulation too ?
If you did not do RTL simulation, please do.
2. Did you see these behavior on your HW only ?
If yes, perhaps DFE setting is not suitable for your system.
DFE needs a random input data to run correctly. If you do not apply any data-scramble on your RAW data, LPM is your only choice.
Thanks & regards
Leo
04-29-2020 04:17 AM
Hello @vt3
1. May I know the Vivado version you are using ?
I will try to reproduce your report and give you feedback on this.
2. Rather unrelated topic.
You are using DFE with insertion loss=6dB. Is there any specific reason using DFE ?
Please read UG576 Chapter4. We suggest to use LPM for short reach channel.
Thanks & regards
Leo
04-29-2020 04:31 AM
Leo,
I'm using vivado 2018.3.1.
Please find attached the .xci file (easier).
The file name may not be the same (GTh_North [RX] and GTH_South [Tx]) and it's with this this I'm stuggling.
As for the DFE I'll have a look, thanks to point it !
Regards
04-29-2020 05:03 AM
Hello @vt3
I generated a Transceiver Example Design with Vivado 2018.3.1 and 2019.2. (with configuration from screenshot above. You did not attach your xci file)
Unfortunately, I cannot reproduce your report.
Transceiver wizard generated RXUSRCLK/RXUSRCLK2 with expected clock period.
RXUSRCLK = 12000/32 = 375 MHz
RXUSRCLK2 = 12000/64 = 187.5 MHz
These are expected clock frequencies.
A few questions for you:
1. Did you see these behavior on simulation too ?
If you did not do RTL simulation, please do.
2. Did you see these behavior on your HW only ?
If yes, perhaps DFE setting is not suitable for your system.
DFE needs a random input data to run correctly. If you do not apply any data-scramble on your RAW data, LPM is your only choice.
Thanks & regards
Leo
04-29-2020 05:11 AM
I'll try to perform a simulation.
Thanks.
I don't know why, but the xci file attachement didn't goes right...
The incoming datas are scrambled with a specific protocol.
Thanks and regards
04-30-2020 02:43 AM
OK after Léo remarks and question I'd "JUST" erase evrything and rebuild a new IP with the same parameters and all is good !
"Did you try to turn it off and on" kind of solution.
Looks like some cache was not cleared !
Thanks and regards