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Adventurer
Adventurer
443 Views
Registered: ‎07-27-2018

XDC for GT clock in VCU1525

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Hi everybody,

I'm trying to use QSP28 VCU1525 for 100G connection CAUI4, I know I need a 161.1328 MHz clock. In particular I want to use

QSFP0 so GT in Bank 231.

As described in UG1268 v1.4 pag 26 "System Clock and QSFP0 Clock":

CLK1A/B: The QSFP0_CLOCK_P/N clock is an AC-coupled LVDS 156.25-MHz clock wired
to QSFP0 interface GTY bank 231 MGTREFCLK1 P/N input pins K11 and K10.

 

schematic.png

Since I would like to set the clock to 161MHz I need to control FS pins.

Where Can I find the constraints for this pins?

Where do you route this lines?

Thank you

 

 

 

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Adventurer
Adventurer
370 Views
Registered: ‎07-27-2018

I managed to solve problem using a 1.0 User Guide of VCU1525 in which all the constraints are reported at the end of the document.

Up to now on the xilinx documentation there is only the v1.3 available.

I really don't understand why not all UG versions are documented.

 

Regards

 

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1 Reply
Adventurer
Adventurer
371 Views
Registered: ‎07-27-2018

I managed to solve problem using a 1.0 User Guide of VCU1525 in which all the constraints are reported at the end of the document.

Up to now on the xilinx documentation there is only the v1.3 available.

I really don't understand why not all UG versions are documented.

 

Regards

 

View solution in original post

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