07-26-2018 06:32 PM - edited 07-26-2018 07:09 PM
I'm configuring an Aurora IP on ZCU102 in TX only mode.
According to Aurora manual, I use 2 BUFG_GT connected to tx_out_clk to generate the clocks for my user_clk and sync_clock.
However the tx_out_clk net failed in the routing, the error is listed as below:
And here is my Aurora configuration, block diagram and the floor planning for tx_out_clk:
The BUFG_GT is instantiated manually to enable its DIV function.
The aurora ip design is basically according to Figure 3-1:
Can anyone help on this?
07-27-2018 11:49 AM
a BUFG_GT symbol should actually look like this:
07-29-2018 08:03 PM - edited 07-29-2018 08:16 PM
Yes, what I did was instantiating it manually to enable the DIV function.
The images below are using the IP directly, the tx_out cannot be fully routed and BUFG_GT in other banks are instantiated:
Then I think instantiating BUFG_GT on other banks may prevent routing, so I delete the two BUFG_GT and get the following results:
Can you help me with this?
Thank you very much.
07-31-2018 10:55 AM
I hope your CE input is driven high and the name is just a '0' there.
Other than that not sure about the clk_wiz_1. You should use the BUFG_GT to drive the user_clk directly.
In your first picture util_ds_buf_0 and clk_wiz_1 are not necessary.
tx_out_clk can drive both BUFG_GT (buf_1 and buf_2). You just need to make sure that the controls for CE and CLR are identical.
The DIV input you can set differently.
Don't leave the inputs unconnected.
Only transceiver primitives can drive BUFG_GT. There are no routes to drive a BUFG_GT from the clocking wizard.
08-03-2018 08:21 AM - edited 08-03-2018 11:01 AM
Yes, I tried what you said at the very beginning. I got the results as shown in the image.
The DIV function is not working. Then I checked the forum and found a solution for this issue(make a wrapper for the BUFG_GT to enable DIV):
I adopted the last solution. It still doesn't work. I'm using Vivado 2017.4.
Can you help me with it? Thank you very much!