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1,035 Views
Registered: ‎07-19-2018

ZCU102 Aurora tx_out_clk failed in place&routing

Hello,

 

I'm configuring an Aurora IP on ZCU102 in TX only mode.

According to Aurora manual, I use 2 BUFG_GT connected to tx_out_clk to generate the clocks for my user_clk and sync_clock.

However the tx_out_clk net failed in the routing, the error is listed as below:

Capture.JPG

 

And here is my Aurora configuration, block diagram and the floor planning for tx_out_clk:

Capture.JPG

 

 

Capture.JPG

 

 

The BUFG_GT is instantiated manually to enable its DIV function.

The aurora ip design is basically according to Figure 3-1:

https://www.xilinx.com/support/documentation/ip_documentation/aurora_64b66b/v11_2/pg074-aurora-64b66b.pdf

 

Can anyone help on this?

 

Thank you.

 

 

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4 Replies
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Xilinx Employee
Xilinx Employee
980 Views
Registered: ‎10-19-2011

hi @zxyxinyizhang,

 

a BUFG_GT symbol should actually look like this:

 bufg_gt_sym.PNG

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952 Views
Registered: ‎07-19-2018

Hello,

 

Yes, what I did was instantiating it manually to enable the DIV function.

 

The images below are using the IP directly, the tx_out cannot be fully routed and BUFG_GT in other banks are instantiated:

1.JPG




2.JPG



3.JPG




4.JPG





 

Then I think instantiating BUFG_GT on other banks may prevent routing, so I delete the two BUFG_GT and get the following results:

NB1.JPG




NB2.JPG




NB3.JPG




NB4.JPG

 

 

Can you help me with this? 

Thank you very much.

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Xilinx Employee
Xilinx Employee
929 Views
Registered: ‎10-19-2011

Hi @zxyxinyizhang,

 

I hope your CE input is driven high and the name is just a '0' there.

Other than that not sure about the clk_wiz_1. You should use the BUFG_GT to drive the user_clk directly.

In your first picture util_ds_buf_0 and clk_wiz_1 are not necessary.

tx_out_clk can drive both BUFG_GT (buf_1 and buf_2). You just need to make sure that the controls for CE and CLR are identical.

The DIV input you can set differently.

Don't leave the inputs unconnected.

Only transceiver primitives can drive BUFG_GT. There are no routes to drive a BUFG_GT from the clocking wizard.

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894 Views
Registered: ‎07-19-2018

Hi @eschidl,

 

Yes, I tried what you said at the very beginning. I got the results as shown in the image.

 

The DIV function is not working. Then I checked the forum and found a solution for this issue(make a wrapper for the BUFG_GT to enable DIV):

https://forums.xilinx.com/t5/UltraScale-Architecture/Utility-Buffer-BUFG-GT-for-clock-divider/td-p/767894

I adopted the last solution. It still doesn't work. I'm using Vivado 2017.4.

 

Can you help me with it? Thank you very much!

2 BUFG GT.JPG

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