ZCU102 IBERT 10Gb Line Rate with Mhz reference clock

[bademcib]

I've some experience with ZCU102 board generating 10Gb/s over SMA loopback with On-Off keying modulation(what scope shows) to perform BER test but documentation shows it's uses reference clock in Mhz level. How is it possible to generate Gigabit Line rate especially 10Gb and above with Mhz reference clock? Someone told me to look at SerDes but I could not make sense with it. Can somebody please navigate me as I'm fairly new in electronics?

[miker · Accepted solution]

@bademcib I would suggest referencing the following documents.  The Zynq UltraScale+ MPSoC ZU9EG includes GTH transceivers which are comprised of GTHE4_CHANNEL and GTHE4_COMMON primitives.  The GTHE4_COMMON primitives include a Quad PLL shared with all GTH Quad Channels and each GTH Channel includes a CPLL.

• UltraScale Architecture GTH Transceivers User Guide (UG576; v1.6)
  • Chapter 2: Shared Features > Reference Clock Selection and Distribution
  • Chapter 2: Shared Features > Channel PLL
  • Chapter 2: Shared Features > Quad PLL
  • Figure 1-1: GTH Transceiver Quad Configuration

• Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925; v1.18)
  
  • Table 101:  GTH Transceiver Reference Clock Switching Characteristics