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Observer
Observer
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Registered: ‎01-24-2019

ZCU102 IBERT GTH Debug Core not working in example design.

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I am working on getting an IBERT Core running using the GTH Example design (IP Catalog --> Ultrascale Transceiver Wizard). After generating the example design and assigning a pin to "hb_gtwiz_reset_clk_freerun_in" and generating the bitstream, when I program the device it shows there is no debug core. I have also verified that the "C_USER_SCAN_CHAIN" and BSCAN_SWITCH_USER_MASK match (1 and 0001 respectively). I have also changed the JTAG Freq from default 15MHz to 6MHz. My question(s) are:
-Shouldn't the example design be drop in (ie. just work OOB with no modification, which I've had to do).
-What do I need to do to get this debug core running (we need to check eye diagrams on 8 channels with a loopback module connected to FMC).


I've attached my xdc file and some images to clarify. I can also upload the whole example project if needed, but it is just the auto-generated example project with the only modifications done is the pin assignments in the top level XDC file for undefined pins.

Thanks,

Thomas Mindenhall

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: ZCU102 IBERT GTH Debug Core not working in example design.

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hi @tmindenh1 ,

another option would be to change the DRP clock in your setup to 125MHz and use the CLK_125_P/CLK_125_N clock of the board (LVDS_25 on G21/F21).

You would need to add an IBUFDS to the example design. This clock is definitely present.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: ZCU102 IBERT GTH Debug Core not working in example design.

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hi @tmindenh1 ,

this is most likely an issue with the system clock / freerunning DRP clock. This must be present with configuration as it is necessary for the debug core detection.
In your case even the dbg_hub itself is not seen.

Where is your 250MHz clock driven from?

Could you maybe switch to the reference clock as the system clock for the core?

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: ZCU102 IBERT GTH Debug Core not working in example design.

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hi @tmindenh1 ,

another option would be to change the DRP clock in your setup to 125MHz and use the CLK_125_P/CLK_125_N clock of the board (LVDS_25 on G21/F21).

You would need to add an IBUFDS to the example design. This clock is definitely present.

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Contributor
Contributor
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Registered: ‎03-19-2019

Re: ZCU102 IBERT GTH Debug Core not working in example design.

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Hello @eschidl,

I'm facing the same issue and I don't understand how to solve it. I'm not using Aurora 8b/10b, I'm creating my own protocol.

Is it possible to have more details ?

Regards,

Emilie

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: ZCU102 IBERT GTH Debug Core not working in example design.

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Hi @emilie ,

the system clock (DRP clock) needed to be connected to a free running clock. If the debug core does not have that it will not be detected on the JTAG chain after configuration.

This is completely independent on what protocol you are running on the link.

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