12-11-2018 08:25 AM
Is it possible to flip the individual P/N polarity of each PS-GTR lane? I haven't been able to find anything but the documentation and this previous forum post: https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Changing-Polarity-of-PS-GTR-Transceivers/td-p/803734
However, I don't see these registers listed in my psu_init.c or the register documentation that comes with my xczu4cg-sfvc784-1-e. What can I do? I know for a fact that the RX signals have their P/N flipped. The TX signals are correct polarity though.
12-14-2018 08:53 AM
You can switch the polarity. You have the address and offset from the UG1087. That is all that is needed. As shown in the other post those addresses can be used to flip the RX polarity only.
12-17-2018 07:07 AM
Hey thank you for the response.
I was actually incorrect, I need to flip the TX polarity, not the RX polarity. Is this possible?
For instance, with this register -- what is the difference between force_TX_swap_polarity and TX_swap_polarity bits?
Can I just write 0x0C to 0xFD400034 to flip the TX polarity?
Also, should I write to this register in psu_init.c or can I do it in the FSBL in xfsbl_board.c?
12-17-2018 03:31 PM
That will work for lane 0. Use L0_TX_ANA_TM_13 to L3_TX_ANA_TM_13 for lanes 0 thru 3 for the TX side. Someone from embedded will need to help with the other part of the question.
12-19-2018 05:31 AM
Yeah, so if I set each lane (0xFD400034, 0xFD404034, 0xFD804034, 0xFD40C034), to 0xC, then I rescan -- nothing else shows up. I do know for a fact that the TX P and N's are swapped, and the RX pins are correctly connected. All the TX's go to RX, and visa versa. By the way, this is on a custom board, not the zcu102.
The REFCLK and PCI CLKs all look good and at 100 MHz. Is there anything I can do to specifically figure out why my device isn't showing up? Are there debug messages I can turn on? Read a log?
I need to look at the lane signal directly, I'm guessing, at this point. I just don't have much experience debugging pcie!
12-19-2018 11:13 PM
is zu4 the root port? what is the end point? Another Xilinx FPGA or something else?
I think you can start with IBERT first.
UG936 Lab10 is an example for ZCU102 board.
12-20-2018 05:32 AM
Hello Boris, thank you for your response!
The zu4 is the root complex and I have an nvme ssd connected as the end point. This configuration works perfectly with the zcu102. My custom board uses a TE0803 (https://shop.trenz-electronic.de/en/TE0803-02-04CG-1EB-MPSoC-Module-with-Xilinx-Zynq-UltraScale-ZU4CG-1E-2-GB-DDR4-256-MByte-Flash) module for the FPGA and I have a custom board that connects the PS-GTR's directly to an M.2 connector to the NVME SSD.
The clocks are all looking good at 100 MHz, PCIe reset look fine, and I'm using the fsbl code to reset the PCIe initially (still MIO31). The only difference is that the TX ports have their polarity swapped (P's and N's, not lanes). RX ports are correctly P->P, N->N.
Would it be much work getting the IBERT fsbl to work with my custom stuff?
12-20-2018 05:59 AM
Please also note that the 100 MHz clocks are being generated by an Si5338A on the custom board, that has been pre-programmed to output 100 MHz for the B505_CLK1 and M.2 CLKREF going to the M.2 connector. I have CLK1 set as the GT Reference clock for the PCIe. I'm using the IOPLL for the 250 MHz to the PCIe controller. Everything should be ready to go... Is it possible the Si5338A isn't outputting its clock fast enough for when the psu_init is writing the pcie registers?
12-20-2018 08:29 AM
One more thing (promise):
In the UG936 Lab, it's saying to make FSBL modifications for the USB 3.0 controller with the USB3_0_XHCI_GCTL register, what registers would I place here to use for PCIe?
01-30-2019 06:51 AM
I finally got the basics of IBERT for PS-GTR running on my custom board. Every eyescan is incomplete. Sometimes I get Linked status for each Link, but it seems pretty random. Hmm. Any ideas for what I should be looking at?