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labluxor8
Observer
Observer
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Registered: ‎08-31-2017

Zynq Ultrascale+ SMA MGT Clock input

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Hi everybody,

 

I have two questions about the two SMA MGT Clock inputs (p and n).

 

- I saw in the User Guide that these two input ports do not have a standard I/O and that they are series-capacitor coupled. As I understand, I can provide a LVDS (18 or 25) clock to these ports, right? I tried to generate a 156.25 MHz clock from a ZedBoard and output the differential clock through the FMC SMA outputs with a Xilinx FMC 105 Debug Mezzanine. I checked the output on an oscilloscope and I saw the two waves with approx. (single wave values) 800 mV offset and 800 mV amplitude (over the offset voltage). Unfourtunatelly, nothing happens when I connect the clock to the Ultrascale and the Transceiver is not working. Are there some specs I'm missing? It is ok with that clock source?

 

- Just to be sure. I need to have a transceiver perfectly edge-synchronized with other hardware logic on the Ultrascale. As I understand, the SI570 oscillators cannot be share between Transceiver Bank and other bank, right? For example, I cannot use the USER_MGT_SI570_CLOCK1_C_P as a clock for my fabric logic. Viceversa, I cannot use the USER_SI570_P as a clock for the transceiver.

 

Thank you very much,

Andrea

 

Note: I noticed that in the UG1182 (table 3-13 page 44) there is an error since the USER_SI570_P(N) are set to be at N27 and N28 pin while they are at J28 and J27 as indicated all around the UG1182 and in the ZCU102 Master XDC file

 

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labluxor8
Observer
Observer
2,743 Views
Registered: ‎08-31-2017

Ok, apperently I found out the solution.

 

I simply missed some specs in the BUFG_GT.

Writing all specs just do the job:

 

BUFG_GT GInst(
     .I(FabricClkBuf),
     .CE (1'b1),
     .CEMASK(1'b1),
     .CLR (1'b0),
     .CLRMASK(1'b1),
     .DIV (3'b000),
     .O(FabricClk)
);

View solution in original post

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roym
Moderator
Moderator
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Registered: ‎07-30-2007

You cannot drive the mgt with any clock that doesn't come into a designated reference clock input but you can use a reference clock input to both drive the mgt and your standard logic.  The IBUFDS_GTE* buffer has 2 outputs as show on page 25 and one of them can drive a BUFG_GT into the Fabric.  For that board you should be good to use the USER_MGT_SI570_CLOCK1_C_P for both the MGT and the fabric.

 

example:

IBUFDS_GTE*  refclkInst(

    .I (userMgtP),

    .IB(userMgtN),

    .O(gtClk),              // drives GTHE*_CHANNEL without further gating (do not run this one through a bufg)

    .ODIV2(FabricClkBuf));

 

BUFG_GT GInst(

             .I(FabricClkBuf),

             .O(FabricClk));   //drives any fabric logic gate

 

 

 

 




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labluxor8
Observer
Observer
2,479 Views
Registered: ‎08-31-2017

Hi roym,

 

thank you very much for your answer.

 

I did what you suggested but after many tries it seems to me that the clock is not coming out from the ODIV2.

 

It is possible that there is a problem with the IBUFDS_GTE4 parameters?

I left the default value for the parameters which are the same indicated at page 26 of ug576
https://www.xilinx.com/support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf

 

I'm talking about REFCLK_EN_TX_PATH, REFCLK_HROW_CK_SEL and REFCLK_ICNTL_RX.

 

What it could be?

 

Thank you,

Andrea

 

 

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labluxor8
Observer
Observer
2,744 Views
Registered: ‎08-31-2017

Ok, apperently I found out the solution.

 

I simply missed some specs in the BUFG_GT.

Writing all specs just do the job:

 

BUFG_GT GInst(
     .I(FabricClkBuf),
     .CE (1'b1),
     .CEMASK(1'b1),
     .CLR (1'b0),
     .CLRMASK(1'b1),
     .DIV (3'b000),
     .O(FabricClk)
);

View solution in original post

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