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1,672 Views
Registered: ‎07-23-2019

Zynq ultrascale+ GTH jitter spec?

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Is there any jitter specification for the GTH transceivers?

So far what I'm doing is select a reference oscillator with "low jitter" that the manufacturer recommends it for my application then trust the GTH will comply with the spec (10 GbE), and of course having proper low noise supplies, bypass, etc.

Is there a way to show someone else something more objective than this "trust me, it will work"?

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1,644 Views
Registered: ‎01-22-2015

@archangel-lightworks 

Table 102 of the datasheet, DS925(v1.16), indirectly gives the jitter specification for the GTH transceiver clock.  That is, Table 102 gives a phase noise mask/envelope for the clock frequency spectra.

According to AR#63026, the phase noise mask is a preferred method for specifying jitter of the UltraScale GTH/GTY reference clock. 

The websites listed below have calculators that help you convert the phase noise mask into traditional time-measurements of jitter.

https://www.silabs.com/jittercalculator/phase-noise-jitter-calculator.aspx 

https://abracon.com/phaseNoiseCalculator.php

https://www.maximintegrated.com/en/design/technical-documents/app-notes/3/3359.html

The phase noise mask/envelope is well understood by manufacturers of quality clock oscillators.  So, when buying a clock oscillator for your project, give them a phase noise mask specification rather than a jitter(time) specification.  

Finally, if you are buffering the clock before sending it to the FPGA, then include the "added jitter" specification of the buffer in your total budget for GTH clock jitter.

Mark

 

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1,645 Views
Registered: ‎01-22-2015

@archangel-lightworks 

Table 102 of the datasheet, DS925(v1.16), indirectly gives the jitter specification for the GTH transceiver clock.  That is, Table 102 gives a phase noise mask/envelope for the clock frequency spectra.

According to AR#63026, the phase noise mask is a preferred method for specifying jitter of the UltraScale GTH/GTY reference clock. 

The websites listed below have calculators that help you convert the phase noise mask into traditional time-measurements of jitter.

https://www.silabs.com/jittercalculator/phase-noise-jitter-calculator.aspx 

https://abracon.com/phaseNoiseCalculator.php

https://www.maximintegrated.com/en/design/technical-documents/app-notes/3/3359.html

The phase noise mask/envelope is well understood by manufacturers of quality clock oscillators.  So, when buying a clock oscillator for your project, give them a phase noise mask specification rather than a jitter(time) specification.  

Finally, if you are buffering the clock before sending it to the FPGA, then include the "added jitter" specification of the buffer in your total budget for GTH clock jitter.

Mark

 

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1,589 Views
Registered: ‎07-23-2019

 

The sharpest, clearest answer ever. Thanks.

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1,579 Views
Registered: ‎07-23-2019

 

There is something I can't square though, in note 2 below table 102 in DS925:

"adjust the phase noise mask values by 20 log (N/312.5)"

So for 100 MHz I get about -10 dB, does that mean I have to add -10 dB to the table figures and make them lower for a lower frequency? That will translate into a lower frequency clock requiring a tighter jitter, is that right?

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eschidl
Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @archangel-lightworks ,

yes, that is correct. To reach the same line rate with a lower reference clock you need a higher multiplication factor for the used PLL. This factor will similarly apply for the noise on the clock. So, to have the same conditions on the serial line, you need a more stringent mask for reference clock with lower frequency.

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1,533 Views
Registered: ‎07-23-2019

 

Makes sense that way. Therefore it looks reasonable to prefer higher frequencies, like 200-250 MHz instead of 100.

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mrbietola
Scholar
Scholar
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Registered: ‎05-31-2012

Hi markg@prosensing.com  i would like to know if i understand correctly. I'm having high low frequency jitter on my board i was looking if choosen  reference clock is correct.

 I would like to double check the calculations with you if possible.

This is the reference clock we use @148.5 https://www.mouser.it/datasheet/2/3/ASEMP-44335.pdf

In Table 102 i found the required jitter phase noise requirement for Ultrascale+ https://www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf

(i summed -6.46 dBc/Hz to the values to take account of the different reference clock frequency)

I inserted the values in the calculator https://www.silabs.com/jittercalculator/phase-noise-jitter-calculator.aspx (as integration bandwidth is correct 10kHz - 1 MHz?)

i found from the calculator a period jitter of  2.76 ps

the oscillator have 2.5 ps (typical)

so if i did the right calculations i have a really tight margin

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Registered: ‎01-22-2015

@mrbietola 

Below is another phase noise calculator that is a little easier to use than the Silabs calculator (although both give similar results).

integrated_phase_jitter.jpg

Into the above calculator, I have entered the envelope data from Table 102 of DS925 after adjusting the values by -6.46 dBc/Hz ( = 20*log(148.5/312.5) per footnote in Table 102.  As you can see from the screenshot, RMS Phase Jitter is calculated to be 908 fs (0.908 ps).

From the datasheet for your MEMS Clock oscillator, and at frequency-offsets of 12kHz - 20MHz from 156.25 MHz, the Integrated Phase Jitter (Jph) is ~2ps.

Since a phase jitter of ~2ps is quite a lot more than 0.908ps, then I think your MEMS Clock oscillator should not be used for the GTH reference clock.

Comparing integrated phase noise (as done above) is just an approximate way to determine whether an oscillator meets the GTH reference clock specifications.  Good manufacturers of oscillators will give you the phase noise spectral plot (dBc/Hz vs offset-frequency) for their oscillator.  Then, as Xilinx intends, you should compare dBc/Hz values from the plot directly to the Table 102 values.

Cheers,
Mark

 

mrbietola
Scholar
Scholar
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Registered: ‎05-31-2012

Hi markg@prosensing.com thanks for your explanation.

I didn't know that the Integrated Phase Jitter  from the datasheet could be referred as Phase Jitter in the calculator, i tought they were different things.

 i redid the calculation with the QPLL values from datasheet (then i don't have the 50 MHZ point in the table) i get 513.9 fs as RMS Phase Jitter.

Does this mean that if i use the QPLL the reference clock should be even more "precise"?

I would like also to know if my previous calculations where i confronted the period jitter were correct. Comparing those values seemed to have margin, but maybe is not the correct parameter to take into account.

 

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Registered: ‎01-22-2015

@mrbietola 

Basic Concepts: 

If we send the output of a sine-wave oscillator to an FFT, then the FFT output gives the power frequency spectrum (W/Hz) of the oscillator.  We would like this spectrum to show a single spike in the FFT bin at your desired (carrier) frequency of 148.5MHz.  However, what we see is a spike at 148.5 MHz and some spectral power near 148.5MHz as shown in the image below.  Then, in simple terms, we integrate the area under the spectrum curve to get RMS phase jitter

phase_noise_plot.jpg

Since we are basically integrating a frequency spectrum, it is odd that our result is called phase jitter and not frequency jitter.  Also, when the frequency axis of frequency spectrum is adjusted to be frequency offset from the carrier frequency and amplitude is rewritten as dB below the carrier power (ie. dBc) then the plot is oddly called the phase noise spectrum of the oscillator.

 

Your Questions:

I didn't know that the Integrated Phase Jitter  from the datasheet could be referred as Phase Jitter in the calculator, i tought they were different things.

Since Table 102 in DS925 is giving you amplitude values for the envelope of phase noise for an oscillator then we must focus on RMS phase jitter.

 

i redid the calculation with the QPLL values from datasheet (then i don't have the 50 MHZ point in the table) i get 513.9 fs as RMS Phase Jitter.  Does this mean that if i use the QPLL the reference clock should be even more "precise"?

Not necessarily.  Since the 50MHz point is excluded from Table 102 for the QPLL specifications then we must assume that this point does not matter.  Perhaps there is something in the FPGA which filters off parts of the phase noise spectrum that are 50MHz away from the carrier (so they don’t contribute to jitter).  DS925 does not discuss this point.

 

I would like also to know if my previous calculations where i confronted the period jitter were correct.

As I mentioned previously, since the Table 102 specifications are for phase noise then we must focus on RMS phase jitter – and not period jitter.  If you search the literature, you will find conversions between RMS phase jitter and period jitter.  In fact, there are many ways that jitter can be specified.