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Visitor rilay
Visitor
491 Views
Registered: ‎06-06-2018

aurora lanes PCB matching

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Hi

Question regarding pcb routing for aurora protocol through GTH x4 lanes (quad) between ultrascal chips (zynq us+ to kintex us)

Does there is rule for timing BONDING between the  lanes TX/RX lanes or no need to bonding between the lanes?

i.e. does needed  to route the 4 lanes  on board with  length matching?

What is the matching need between the 4 lanes?

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Xilinx Employee
Xilinx Employee
412 Views
Registered: ‎08-07-2007

回复: aurora lanes PCB matching

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hi @rilay

 

The allowed skew depends on the lane to lane deskew buffer depth.

In Aurora 8b10b mode, the skew is solved by channel bonding in Elastic Buffer in GTH.

In Aurora 64b66b mode, the skew is solved by channel bonding in a Fabric buffer (i.e.,  Async FIFO in BRAM). not inside GTH.

For Aurora 8b10b, you can use the numbers (SMO and SMI) in the tables in sp002. For e.g., SMO is 1000 ps and SMI is 24 ns. This is very big value which is easy to meet. (SMO = Skew at the transmitter output between lanes of a multi-lane channel; SMI = Skew at the receiver input between lanes of a multi-lane channel )

For Aurora 64b66b, I don't see the spec. It should be equavalent as 8b10b.  1 inch mismatch is safe.

 

Thanks,

Boris

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Xilinx Employee
Xilinx Employee
433 Views
Registered: ‎08-07-2007

回复: aurora lanes PCB matching

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hi @rilay

 

Aurora has lane to lane de-skew logic in the PCS layer.

commonly you don't need to worry about the skew caused by the routing length mismatch.

I don't have an exact number for the limit of Aurora 64b66b. If you keep the lane to lane routing length variation in 1 inch, I think it will be fine.

If you are using Aurora 8b10b, you can use the number in Table 6-1 through Table 6-6 of the following document.

https://www.xilinx.com/support/documentation/ip_documentation/aurora_8b10b_protocol_spec_sp002.pdf

 

Thanks,

Boris

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Visitor rilay
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426 Views
Registered: ‎06-06-2018

回复: aurora lanes PCB matching

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Hi

accordimg UG-576 "RX Channel bonding":

"Channel bonding cancels out the skew between GTH transceiver lanes by using the RX
elastic buffer as a variable latency block."

and " RX channel bonding supports 8B/10B encoded data but does not support these encoded
data types:"
• 64B/66B

so.. according UG-576:

8b/10b no need match PCB length between lanes?

and

according your answer match of about 1 inch for 64B/66B ?
 

Thanks

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Xilinx Employee
Xilinx Employee
413 Views
Registered: ‎08-07-2007

回复: aurora lanes PCB matching

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hi @rilay

 

The allowed skew depends on the lane to lane deskew buffer depth.

In Aurora 8b10b mode, the skew is solved by channel bonding in Elastic Buffer in GTH.

In Aurora 64b66b mode, the skew is solved by channel bonding in a Fabric buffer (i.e.,  Async FIFO in BRAM). not inside GTH.

For Aurora 8b10b, you can use the numbers (SMO and SMI) in the tables in sp002. For e.g., SMO is 1000 ps and SMI is 24 ns. This is very big value which is easy to meet. (SMO = Skew at the transmitter output between lanes of a multi-lane channel; SMI = Skew at the receiver input between lanes of a multi-lane channel )

For Aurora 64b66b, I don't see the spec. It should be equavalent as 8b10b.  1 inch mismatch is safe.

 

Thanks,

Boris

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Visitor rilay
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Registered: ‎06-06-2018

回复: aurora lanes PCB matching

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thank you!

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