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ahmad.zaklouta
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Registered: ‎03-07-2018

drive drp clk in kc705

I am designing a SATA core with MIG ddr3 using kc705 board. 

I have a 150Mhz ref clk for GTX and 200Mhz for ddr3 MIG. drp clk is 1..175 Mhz and it is used to clock reset fsm for GTX so I cannot use the 200MHz clk.

Can I use the ref clk 150Mhz by routing it with BUFG from the output of IBUFDS_GTE2 to clock drp and the reset machine?

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karnanl
Xilinx Employee
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Registered: ‎03-30-2016

Hello @ahmad.zaklouta 

>Can I use the ref clk 150Mhz by routing it with BUFG from the output of IBUFDS_GTE2 to clock drp and the reset machine?

It should be fine.
Please let me know if you have any error message during implementation.

Regards
Leo

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ahmad.zaklouta
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Registered: ‎03-07-2018

@karnanl
Is it ok to use 200 MHz clk only to drive both GTX and MIG and configure the CPLL in GTX to output 150 MHz required for SATA3?
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karnanl
Xilinx Employee
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Registered: ‎03-30-2016

Hello @ahmad.zaklouta 

CPLL output is only connected to GTX, you cannot use directly with user logic. See belowCPLL_OUtput.png

But you can use TXOUTCLK for your logic.
The TXOUTCLK frequency depends on your GTX configuration. I would suggest to simulate your GTX example design, to find out the TXOUTCLK freq.



Regards
Leo

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ahmad.zaklouta
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Registered: ‎03-07-2018

@karnanl 

thanks for replying

SATA3 requires 150 MHz to operate with line-rate 6Gb. and ddr3 requires 200MHz. and my design is operating on 150MHz from the TXOUTCLK. so I am thinking to configure the CPLL to accept a 200MHZ and this is a valid option.

I wonder if I took 200MHz after IBUFDS_GTE2 to MIG IP like the picture below, would this be ok or MIG and GTX should have separate clock source.

 

CPLL_OUtput.png

 

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karnanl
Xilinx Employee
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Registered: ‎03-30-2016

Hello @ahmad.zaklouta ,

Using Transceiver wizard, you can configure your GTX to receive 200MHz REFCLK and output 150MHz TXOUTCLK.
No issue on this.

But, I don't think you can use 200MHz REFCLK to feed MIG reference clock, It will not work since MIG will requires you to use a particular pin for a reference clock.
If you have a MIG related question you can post a question on : https://forums.xilinx.com/t5/Memory-Interfaces-and-NoC/bd-p/MIG

Kind regards
Leo

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