12-05-2018 07:50 AM
I have a problem with several PRBS Pattern.
I use a FPGA ARTIX 7 XC7A200T with IBERT V3.0 and VIVADO 2018.2.
I use connexion between GTP213 AND GTP113 of the same FPGA (only one board) in none loopback mode (direct connexion). I use GTP at 3.125Gbps.
1/ With Fast, clk, slow clk and PRBS-7 pattern i have no problems. Link seem to be perfect with no ERROR and very low BER.
2/ But when i use PRBS-15, PRBS-23 or PRBS-31 i have a lot of error that appears (i correctly reset tx and rx path and ber counter).
link cannot be used with these pattern because error is too high.
I know that PRBS-7 would be stressing the link less than the PRBS-15 but i'm very surprise by the difference in error.
in UG482, table 3-12 it's note that : "PRBS-15 is often used for jitter measurement because it is the longest pattern the Agilent DCA-J sampling scope can handle".
How i can confirm that it's a jitter problem, or Something else ?
1/ My cable is new (never used) and only 1 meter and can be used up to 6.6Gbps.
2/ I check TXURSCLK and RXUSRCLK and value are equal and good so CDR is locked for me and confirm that cable is good (see picture in attachment).
3/ I try to work at a lower frequency 0.781Gbps, but problem is similar.
Someone can help me about origin of the problem?
12-05-2018 08:46 AM - edited 12-05-2018 08:56 AM
When you go into PRBS15 mode are you doing another reset of the RX only? If not you should try it. Also it would be good to see what the eye plots look like. One other thing to test is just setting all of the equalization in hold mode when your in PRBS-7 and then switch to PRBS-15. See page 139 of UG482. Somehow you must be entering the wrong frequency for the system clock since the line rate appears wrong. Since this could be an overequalization type problem you should also see if lowering the amplitude helps.
Put the transceiver in NE PMA loopback mode and see how in performs.
12-05-2018 09:11 AM
1/ When i go to PRBS-15 mode, i always reset TX, after Rx and finally BER counter. Always in this order.
2/ In Near-end Mode all is ok (PMA and PCS), communication without errors.
3 / For others tests, i will come back with response........
12-05-2018 09:37 AM - edited 12-05-2018 09:38 AM
I don't think this is the problem but you should reset TX then RX then BER. This might be what you are trying to say.
12-05-2018 10:59 AM
So i did the test :
**** About Reset :
Yes i reset all.
1/Mode or parameter modification
2/ TX RESET
3/ RX RESET
4/ And finally BER RESET
**** About eye plot :
eye plot seem to be good and is visible in attachment . only in PRBS-7 because in PRBS-15 i cannot have 1E-5 (minimum BER of the plot).
**** equalization in hold mode
In hold mode RXLPMHFHOLD = RXLPMLFHOLD = '1' a lot of error appear in PRBS-7 mode. it's the same thing in PRBS-15. Communication don't work with the 2 mode (with a reset of tx , rx and ber).
if RXLPMHFHOLD and RXLPMLFHOLD becomes null again PRBS-7 Mode work well but not PRBS-15.
**** Line rate appears wrong :
The line rate is good. In first post i noted that i reduced the frequency (0.781Gbps) in the goal to be sure that it's not a cable problem. When system will works @ 0.781Gbps, i will change GTP @ 3.125Gbps.
**** lowering the amplitude.
If you speak about TX DIFF SWING. I try to reduce the amplitude but a minimum of 682mv is needed. In my case fpga is not connected directly to connector but to a linear repeater like picture in attachment. Reduce the amplitude don't change anything.
**** Near end mode
In near end mode (pma -pcs) all work well. I don't have errors in the 2 cases.
So i don't know what it's the problem. Is it necessary to configure some registers in NONE loopback mode.
In ug482, page 67, we can see the conditions for far end and near end mode but Nothing is note for none mode?
12-05-2018 11:19 AM
What does a signal integrity analysis of your pcb, cables, connectors show? All perfectly matched? No reflections, discontinuities in the impedance of the differential path? The channel should have 0 BER (no errors). Errors (any at all) indicate your path is not 100 ohms differential, not terminated properly, or being interfered with (cross talk).
12-06-2018 04:31 AM
Signal integrity was done for 6.6Gbps, impedance @ 100 ohms +/-10%, all INPUT / OUTPUT are AC coupled like it's mentionned in datasheet of our linear repetear.
For me it's not a pcb problem. And in this case, problem appears @0.78125 Gbps and it's a very low frequency.
Reflections and Discontinuities generate errors in data and here PRBS-7 mode works extremely well.
**** I did more test @ 3.125Gbps.
** I configured the IBERT GUI in the goal to have the same clock for the 2 quad (it was not the case in first test). Results is a little better.
** I also adjust some parameters like EQ, Output voltage setting of linear repeater.
Now, i have some link (not all) with 0 error in PRBS-15 mode.
So now i can create 2D EYE SCAN and result is very Strange.
In attachment we can see the scan with PRBS-7 pattern and PRBS-15 pattern.
With PRBS-15 pattern a problem seem to be appear with positive VOLTAGE (code).
I'm not very familiar with 2D eye scan.
is someone can give me more information about parameters that can create this type of scan?
12-06-2018 07:10 AM
Check your configuration of the GT input termination,
Looks like you have an offset in amplitude, perhaps the common mode voltage is not being supplied when using AC coupling. Short patterns have less DC shift, so longer sequences will drift out of range (away from 1/2 vcc).
12-06-2018 10:55 AM
It's more complicated because i have 3 differents termination.
1/ GT input termination between fpga Rx and linear repeater.
2/ Repeater Input termination between Linear repeater and FPGA tx.
3/ Repeater input termination between the 2 linear repeater.
I need to know where the problem can be. About FPGA, input termination is 800mV (programmable termination) .
But i see that capacitor value (ac coupling) of my board is very low : 220pF.
In UG482, recommendation is approximately 100nF (as picture in attachment).
Is it possible that a low capacitor value generate this problem ?
I'm not sure that only the capacitors can generate a so big difference between PRBS7 and PRBS15 ?
12-06-2018 11:03 AM
The series capacitor value must be large enough to effectively block DC changes as a result of the data pattern. It also needs to be large enough at the lowest frequency of the data to not cause an impedance miss-match. 100 nf is a commonly used, meets all requirements value. You should use it.
12-06-2018 03:06 PM
I will try to modify the PCB in the goal to check if it's my problem before to accept as solution.