10-18-2019 06:48 AM
Can we connect two FPGAs using MGTTXN0_123(TX-),MGTTXP0_123(TX+) pins of FPGA1 and MGTRXN0_123(RX-),MGTRXP0_123(RX+) pins of FPGA2 without using MGTREFCLK0N_123 and MGTREFCLK0P_123 pins. I am using Spartan 6 FPGA, XC6SLX150T.
10-18-2019 04:13 PM
Could you clarify your question
What is your data rate?
Do you want to run GT without any clock? Or you dont want to use specific pin as a clock source?
10-18-2019 05:04 PM
I have not decided about data rate. I want to test these signals now (interconnection test). But I am not sure how to test these signals.
10-18-2019 11:22 PM
Have you seen locked signal of clock? (Cpll or qpll)
What data do you send on the link?
Could you recieve or monitor data with ila?(chipscope)
10-19-2019 11:18 PM
You can't run GT core without any Refclk given. To establish a communication between two boards you need to setup the GTPs and then be careful about the data encoding to lock the plls.