08-03-2020 12:53 AM
Hi, I have a custom board with kcu160 fpga.
I want to bridge fpga from PC to SSD:
PC <=sata3=> (gt0) kcu160 (gt1) <=sata3=> SSD
I used a gtx IP with state machine based on below code:
link between fpga and SSD configured correctly; but link between PC and fpga doesn't configured.
I dont have any signal (comreset or cominit) on IP. I think the link is dead!
When I turn on my PC, I connect a SSD to sata port for configure sata. I checked the tx pins with oscilloscope and I saw some signals on it. I think its comreset received from PC, but I cant detect it in IP.
Any body can help me how can I detect cominit or comreset in gtx IP base on OOB and device position?
08-03-2020 02:58 AM
>I used a gtx IP with state machine based on below code:
It seems that the code is created for Virtex-5 transceivers.
I can see these code is using RXELECIDLE signal for handshake procedure.
>I have a custom board with kcu160 fpga.
What is KCU160 , I cannot find it in device list. ( Is it Kintex UltraScale ? or 7-series ? )
Anyway RXELECIDLE for both devices (GTX/GTH/GTY) are not useable for line-rate above 2.5Gbps.
Please see also UG476/UG576/Ug578 "RX Out-of-Band Signaling" section.
RXELECIDLE may not behave as expected if the line-rate is above 2.5Gbps.
08-03-2020 09:16 PM
Hi @karnanl . thanks for reply.
I use xc7k160tffg676 (gtx 7 series). sorry! kcu160 was my mistake.
You are write, but I can't detect any signal on any pins of gtx IP from PC for start link. I send cominit with assert tx_cominit pin of IP, but I cant receive anything!
I dont have any problem from FPGA to SSD for creation link. All of pins (comminit,comwake, rxelecidle, etc) work correctly.
08-04-2020 11:59 PM
>PC <=sata3=> (gtx0) Kintex-7 (gtx1) <=sata3=> SSD
I see, so the blue side is okay, but the red side has an issue.
Could you please use oscilloscope to compare OOB signal from PC and SSD ?
Is there any difference on the OOB signal (swing-level, burst-rate, gap-width) ?
Is RXELECIDLE asserted on gtx0 ?
08-11-2020 10:03 PM
Hi, I used the new sata cable and its worked!
But I have now another problem.
In device mode (PC <=> FPGA), when I transmit comwake and after that send align signal (x"7b4a4abc"), I receive "4a4a4a4a" and after receive some other data and after that cominit signal and start again!
After rxelecidle0 deasserted, rxdata and rxcharisk were undefined!
In sata3 standard whan device transmit align signal, Host should transmit align signal and link start. but I don't know why I don't receive align signal.
Can you help me? thank you.
08-12-2020 01:39 AM
Did you try to assert RXCDRHOLD before sending COMINIT,
and deassert RXCDRHOLD after receiving COMWAKE ?
Please see also explanation mentioned in UG476 below that we do recommend to assert GTRXRESET after deasserting RXCDRHOLD.