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tigi
Contributor
Contributor
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Registered: ‎01-17-2018

how to verify placement of GT ?

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I am trying to do a design with multiple GTs, using an "advanced" technique, where i overwrite the LOC constrains of the automatically generated xdc files, with my user xdc file.

After generating the bitstream, how can i verify in vivado where my GTs have been placed ?

I cannot find this information on any report file, nor opening the implemented design in vivado.

 thanks

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barriet
Xilinx Employee
Xilinx Employee
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Registered: ‎08-13-2007

Indeed, report_io will list all of the pins in the package - including those you didn't use and those you did.

Look at the second column "signal name" to find ones that are non-empty. The ones I listed above weren't used - but was an example on what to search for .

Here's a few from an example design that are used (note that this is ZU+ MPSoC so it includes both PS-side GTR and PL-side GTH)

=


| AB36 | GEM0_MGTRTXP0 | | PS_MGTRTXP0_505 | PSS IO | | | | | | Ohm | | | | | | | | | | |
| AB37 | GEM0_MGTRTXN0 | | PS_MGTRTXN0_505 | PSS IO | | | | | | Ohm | | | | | | | | | | |
..
| AD1 | ETH1_10G_KR_GT_RX_gt_port_0_n | | MGTHRXN0_226 | INPUT | | | | | | NONE | NONE | | FIXED | | | | NONE | | | |
| AD2 | ETH1_10G_KR_GT_RX_gt_port_0_p | | MGTHRXP0_226 | INPUT | | | | | | NONE | NONE | | FIXED | | | | NONE | | | |

 

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roym
Moderator
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Registered: ‎07-30-2007

You can see the placement of the GT's in the device view of the open implemented design.  




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barriet
Xilinx Employee
Xilinx Employee
247 Views
Registered: ‎08-13-2007

You should also see these if you run report_io from TCL console, e.g.

...

==
2. IO Assignments by Package Pin
--------------------------------

+------------+-------------------------------+------------------+-----------------------------------+---------------+-----------------+---------+------------+-------------------------+------+-------------------+----------------------+---------+------------+-----------+----------+----------+------------------+--------------+-------------------+--------------+
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Output Impedance (ohms) | Slew | Input Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
+------------+-------------------------------+------------------+-----------------------------------+---------------+-----------------+---------+------------+-------------------------+------+-------------------+----------------------+---------+------------+-----------+----------+----------+------------------+--------------+-------------------+--------------+
| A2 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | |
| A3 | | | MGTHRXN3_231 | Gigabit | | | | | | | | | | | | | | | | |
| A4 | | | MGTHRXP3_231 | Gigabit | | | | | | | | | | | | | | | | |

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tigi
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Registered: ‎01-17-2018

@barriet 

 

i have run report_io on vivado2019.1, on my Kintex US project.

However, it returns a list which contains all MGTH, including MGTH which i do not use in the project.

 

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barriet
Xilinx Employee
Xilinx Employee
222 Views
Registered: ‎08-13-2007

Indeed, report_io will list all of the pins in the package - including those you didn't use and those you did.

Look at the second column "signal name" to find ones that are non-empty. The ones I listed above weren't used - but was an example on what to search for .

Here's a few from an example design that are used (note that this is ZU+ MPSoC so it includes both PS-side GTR and PL-side GTH)

=


| AB36 | GEM0_MGTRTXP0 | | PS_MGTRTXP0_505 | PSS IO | | | | | | Ohm | | | | | | | | | | |
| AB37 | GEM0_MGTRTXN0 | | PS_MGTRTXN0_505 | PSS IO | | | | | | Ohm | | | | | | | | | | |
..
| AD1 | ETH1_10G_KR_GT_RX_gt_port_0_n | | MGTHRXN0_226 | INPUT | | | | | | NONE | NONE | | FIXED | | | | NONE | | | |
| AD2 | ETH1_10G_KR_GT_RX_gt_port_0_p | | MGTHRXP0_226 | INPUT | | | | | | NONE | NONE | | FIXED | | | | NONE | | | |

 

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tigi
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Registered: ‎01-17-2018

@roym 

the open implemented design view has an enormous amount of graphical information, and in vivado 2019.1 i do not find how to search for specific signals on the graphical "Device" view (there is no "search" box as far as i can see).

My GT cores are deep down in my source hierarchy. In the Hierarchy tab (Netlist tab)  I had to find the GT core and then , again deep inside the automatically-generated GT core, i found a "Leaf cell" named: gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST .

On the cell Properties windows i have found its physical location in a field named "Site" .

This is the information i was looking for, however it is a cumbersome procedure, if you imagine that you have a design with dozens of GTs.

I would consider this more a work-around then a solution.

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barriet
Xilinx Employee
Xilinx Employee
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Registered: ‎08-13-2007

@tigi 

There are some automated ways to search the hierarchy pretty quickly.

For example for MPSoC (with US+ GTH), you can enter this in the TCL console
show_objects -name find_1 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == ADVANCED.GT.GTHE4_CHANNEL } ]
This will return a GUI list off all of the primitives here anywhere used in the design

Simply click on any of them and you can inspect the associated properties
for example
LOC GTHE4_CHANNEL_X0Y0
but I'll admit that is the internal coordinate - there's also the bank # and external package pin #s.

That's why use the report_io if I want external #s.

But there's other cool TCL tricks that can be somes useful like:
get_sites [get_package_pins -filter { PIN_FUNC =~ *MGTHTXP0_225* }]

get_package_pins -filter { PIN_FUNC =~ *MGTHTXP* }

get_package_pins -filter { PIN_FUNC =~ *MGTHRXN* }

get_iobanks -filter {BANK_TYPE == BT_MGT}

But report_io will a follow-on search for "MGT" or "GTH" is usually where I start

tigi
Contributor
Contributor
127 Views
Registered: ‎01-17-2018

regarding the solution that i accepted from barriet (post-placement IO report), this is useful only if the MGT lanes are explicitly connected and declared as IOs in the top level design file. this is the recommended way to do things, however you can generate the bitstream file even without doing it. In this case the post-placement IO report will not contain the information i requested.

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roym
Moderator
Moderator
104 Views
Registered: ‎07-30-2007

Barrie's method will normally be the fastest but you should probably turn off the automatic wizard placement (with the instructions I sent) so you can simply put the normal loc instructions in the top level XDC file.  Just FYI to find the used GT's in the implemented design use ctrl-f to open the find dialog then choose GT as shown below.




----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
Be sure to visit the Resources post periodically to keep up with the latest
https://forums.xilinx.com/t5/Serial-Transceivers/Serial-Transceiver-Forum-Guidelines-and-Useful-Resources/td-p/1173590
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Find.JPG