07-10-2019 09:24 AM - edited 07-10-2019 09:24 AM
We have a multi-Kintex FPGA design that is using Aurora 64/66 protocol channels to communicate between FPGAs. We're running these at 6Gbps.
We used iBerts to test these channels initially, but we would like to test and fine-tune these now. Unfortunately, we can only seem to get the iBert up to 2.97Gbps. We have QPLL's running at 148.50MHz and a system clock of 200MHz. Configuring the iBert IP says that the channels should be running at 5.94Gbps, but they are not. Only 2.97Gbps.
I downloaded Vivato 19.1, and re-built everything from the example design. No Joy.
What are we doing wrong here?
07-10-2019 10:45 AM
Normally the issue here is specifying the wrong frequency of the system clock that is used measure the output frequency. I normally use the reference clock (internal clock) as the system clock and avoid this complication. I haven't seen a case where the measurement wasn't the problem.
07-10-2019 02:09 PM - edited 07-10-2019 02:09 PM
I changed both the sending side and the receiving side system clock source to be Quad115_0. I'm assuming this is MGTREFCLK0.
The receiving side now says 4.000Gbps. Still not 6. Also, it doesn't matter what the sending side is set to, the receiving side always says 4.000Gbps.
This is nuts. This should really work - and easily too.
07-10-2019 04:18 PM
Are you using the pre-built exampel design or were there design modifications?
07-11-2019 12:07 PM - edited 07-11-2019 04:23 PM
No modifications - just the example design. Pretty simple top level - version 2012.3: I/O declarations, signal declarations, IBUFDS instantiations for refclk0_i, refclk1_i, and sysclk_i, ibert_7series_gtx_0 instantiation.
07-11-2019 04:00 PM - edited 07-11-2019 04:01 PM
I'm afraid only the unmodified example design is supported. It mostly doesn't work with modifications of any kind.
07-11-2019 04:22 PM - edited 07-11-2019 04:24 PM
I just said that I DID NOT modify the example design.
(I just edited my earlier reply to more clearly reflect that.)