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Visitor
Visitor
1,090 Views
Registered: ‎03-13-2018

ibert gth working on one bank only

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HI,

I have virtex 7 fpga (XC7VX690tffg1157-2) with gth transceivers.

I am using the ipcore of ibert and create example design and run implementation on it.

when i used the ibert ip core to generate prbs on bank 115 ch0 (I have one rx and one tx on board), and I make external loopback using cables its working ok (refclk is refclk1 of bank 115)

when i used the ibert ip core to generate prbs on bank 117 ch3 (I have one rx and one tx on board), and I make external loopback using cables its working ok (refclk is refclk1 of bank 117)

when I ewant to check both banks at the same time I am using the ibert ip core and use same setup I used for both IP's with the following changes:

1. number of protocols is now 2

2. eqch protocol has one quad count and quad pll is selected since the datarate is 11.264Gpbs

3. in protocol selection tab i select for QUAD_115 and QUAD_117 the same settings as I did for each one before but select different protocol for each one (since I have 2 identical protocols)

4. clock setting tab is the same (external lvds clock i have in the board)

 

when doing the example design of this one and implementing it, there are no links!!

 

is there a problem running 2 protocols in two different banks (each with its own refclk) with the ibert ip?

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Xilinx Employee
Xilinx Employee
1,039 Views
Registered: ‎11-29-2007

hello

no it is expected to work.

please make sure to use latest Vivado release

please double check power supplies.

You might try a lower datarate first.

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Xilinx Employee
Xilinx Employee
1,040 Views
Registered: ‎11-29-2007

hello

no it is expected to work.

please make sure to use latest Vivado release

please double check power supplies.

You might try a lower datarate first.

View solution in original post

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Visitor
Visitor
1,021 Views
Registered: ‎03-13-2018

Hi,

I made another simple test and got the following results:

I made a ibert core with low datarate, one costume interface for two quad tranceivers block (118, 117). refclk inputs at refclk1 of bank 117. system clock from external lvds input (pins W30,W31 if its important), with internal diff termination.

when vivado was connected to the device (after programming) , I manual created all the links.

I started to place loopback in bank 18 links and everything was working great. added one loopback in back 117 and still ok (so far 5 links are working with no errors).

the next loopback i entered to bank 117, cause all the link to go to no link condition. turning the loopback to off, return the 4x bank 118 links to order (rx,tx reset was needed) but the link in bank 117 remain in no link state.

its seems like there cant be more then 5 links in two bank on the same refclk.

1. i will check power when this happens and inform you if there is an issue there.

2. is this a limitation with the ibert code?

I am using the latest bert ip (I think rev 3.0). vivado is not the latest, but if the ip is ok , should there be a problem (vivado 2017.4)?

 

thanks!!!!!

 

 

 

 

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Xilinx Employee
Xilinx Employee
995 Views
Registered: ‎11-29-2007

great to know all is fine now.

yes it could be a resolved bug with old IBERT code.

 

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Visitor
Visitor
888 Views
Registered: ‎03-13-2018

HI,

found the problem as you suggested in the power (was onboard current limit by mistake that reduced the power to lower then 1.05V)

thanks!!

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