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Participant
Participant
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Registered: ‎12-28-2014

jesd204b rx_core_clk ratio

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My question is about the documentation's core_clk frequencies.  Why is the _core_clk frequency /66 in the JESD204 PHY v4.0 docs and /40 in JESD204 v7.2 docs? 

tx_core_clkIn Core clock used to drive txusrclk and txuserclk2 of transceiver.Frequency = serial line rate/66

rx_core_clkIn Core clock used to drive rxusrclk and rxuserclk2 of transceiver.Frequency = serial line rate/66

rx_core_clkIn Core logic clock.Frequency = serial line rate/40

I was pretty confident that the PHY core needs to run at /40 also - hence the syncronous path between the two cores.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @mowerj ,

there are two entries for the clocks in pg198, one for JESD204C (/66) and one for JESD204B (/40). So, depending on the JESD version you get a different divider because a different encoding is used in the PHY.

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Xilinx Employee
Xilinx Employee
357 Views
Registered: ‎10-19-2011

Hi @mowerj ,

there are two entries for the clocks in pg198, one for JESD204C (/66) and one for JESD204B (/40). So, depending on the JESD version you get a different divider because a different encoding is used in the PHY.

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