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110 Views
Registered: ‎10-30-2018

looking for spec for the Ultrascale GTH TXCTRL0 and TXCTRL1 ports

The Ultrascale GTH document UG578 specifies that the ports of TXCTRL0 and TXCTRL1 ports of GTH are used for

1) controlling tx running disparity, or

2) extending the data port to 20,40,80 bits

But in the GTH wrapper code, pcie_ultrascale_ep_gt_channel.v created from vivado, they are used for Gen3 block alignment output signals as below 

//--------------------------------------------------------------------------------------------------

//  Input Port Remapping

//--------------------------------------------------------------------------------------------------   

assign txdata[ 31: 0] = GT_TXDATA;

assign txdata[127:32] = 96'd0;

 

assign txctrl0[ 1:0] = 2'd0;

assign txctrl0[   2] = GT_TXDATA_VALID;

assign txctrl0[   3] = GT_TXSTART_BLOCK;

assign txctrl0[ 5:4] = GT_TXSYNC_HEADER;

assign txctrl0[15:6] = 10'd0;

 

assign txctrl1[   0] = GT_TXCOMPLIANCE;

assign txctrl1[15:1] = 15'd0;

 

assign txctrl2[ 1:0] = GT_TXDATAK;

assign txctrl2[ 7:2] = 6'd0;

 

I searched the Xilinx document and could not find any descriptions for this mapping. Please advise where is the document for it?? Since my design need to control the running disparity, but the document looks not matching with the wrapper code?

Thanks,

Xiao

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2 Replies
Moderator
Moderator
29 Views
Registered: ‎02-16-2010

Re: looking for spec for the Ultrascale GTH TXCTRL0 and TXCTRL1 ports

Hi wangxiao@skhms,

With PCIe, the TXCTRL0 and TXCTRL1 ports are used with multiple purposes based on the line rate at which PCIe link operates. They will be used differently based on the link rate. TXCTRL0 and TXCTRL1 ports should have been used to control running disparity at Gen1/Gen2 rates and for block alignment at Gen3 rates.

Can you simulate the PCIe IP example to understand the role of TXCTRL0 and TXCTRL1 ports?

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Xilinx Employee
Xilinx Employee
13 Views
Registered: ‎08-07-2007

回复: looking for spec for the Ultrascale GTH TXCTRL0 and TXCTRL1 ports

hi wangxiao@skhms

 

Please check UG576 Table 3-7 on page 112 for the mapping info between TXCTRL* and TXDATA.

Please check Table 3-6 for the disparity mapping info with TXCTRL0 and TXCTRL1.

With above information, I think you can control the disparity as you wanted.

http://www.xilinx.com/support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf

 

Thanks,

Boris

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