01-09-2019 05:54 AM
My board has two xc7v690t, the FPGA A is conneted to six ADCs via JESD204, each ADC using four GTH lanes.
The two FPGAs are connected using 16 GTH lanes.
The FPGA A could run JESD204 or 16 GTH lanes independently, while these two function block were adding into the FPGA simultaneously, the 16 GTH lanes run failed.
How to solve this problem?
01-14-2019 06:20 AM
there might be many reason for this (PCB issue, power supply, REFCLK, wrong clock tree, reset issue ... ). Have you tried with IBERT? In this way we will debug the REFCLK, the power and the layout with one test.