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problem of SRIO

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Visitor
Posts: 7
Registered: ‎03-14-2018

problem of SRIO

I have a project to use 5G SRIO, I run a SRIO example on V7 485t in Xilinx, on 7z045, and under ise and vivado software, and the tests and phenomena are as follows:

When connecting 5G SRIO, the link_ok signal should be pulled down from time to time, and then it will pull up again very soon.
When connecting 3.125G SRIO, the connection is normal, and the link_ok signal is always high.
I suspect that the wiring and clock affect the quality of the signal. So link test was done with ibert. It was found that the signal of 5Gbps is good, and there is no error code.
When I reconfigured the CDR of ibert according to the CDR configuration of GTX in SRIO, there were many error codes.
Then, I copy the CDR parameter in ibert is to the GTX CDR parameter of SRIO, and the link_ok signal of SRIO is always low.
is there any one who can provide some solutions? I can't see where the problem is. Thanks a lot.

Moderator
Posts: 411
Registered: ‎07-30-2007

Re: problem of SRIO

You are using an example design from the GT wizard?  Assuming you are using an external loopback I would suggest using an NE PMA loopback mode and get that working first.

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Xilinx Employee
Posts: 237
Registered: ‎11-29-2007

Re: problem of SRIO

hello,

is it possible that also the TX cursor/precursor/postcursor setup is different in IBERT? how is the RX equalizer set in IBERT and SRIO design?

 

 

Voyager
Posts: 661
Registered: ‎02-24-2014

Re: problem of SRIO

Go back to the IBERT test and do some testing with PRBS31 patterns.    Find the GTX TX & RX parameters that give you the best eye opening.   You may have to modify the TX swing, pre and post ambles, along with adjusting the DFE or LP in the RX.  I've seen cases in the GTX where the DFE doesn't work well, because the RX signal is too strong, and it overloads the receiver circuits.

 

Once you get a really nice reliable eye diagram with IBERT, then copy these parameters over to the SRIO core.

Visitor
Posts: 7
Registered: ‎03-14-2018

Re: problem of SRIO

thank you for reply,

I used an example design from the SRIO,the two board be connected by a 4x fibre,so it can not work in external loopback mode

Visitor
Posts: 7
Registered: ‎03-14-2018

Re: problem of SRIO

thank for your reply ,

I tried to change the  TX cursor/precursor/postcursor setup,but if I copy the CDR paramater in ibert which is work well to SRIO setup,then whatever I change the TX cursor/precursor/postcursor ,the SRIO link_ok signal will never go high,

when I use the CDR paramater in SRIO example design,then I treid many TX cursor/precursor/postcursor parameter ,the link_ok signal also pull down time by time.

Visitor
Posts: 7
Registered: ‎03-14-2018

Re: problem of SRIO

thanks for your reply

I use the ibert sweep scan mode ,to find a nice eye diagram,then copy the best paramater to srio setup,but it doesn't work well too,

I check the source code in SRIO example ,find that the 3.125G SRIO use QPLL in gtx,but 5G SRIO use CPLL,why?

can I use qpll in 5G SRIO.

 

Xilinx Employee
Posts: 237
Registered: ‎11-29-2007

Re: problem of SRIO

hello,
the CPLL (output divider = 1) can be used for rate of 5Gbps for any speed grade.
the QPLL range 2  only and output divider = 2 supports 5Gbps only for speed grades -2 and -3.
It might be just a choice based on the CPLL flexibility, I have not found information on the reason of this original choice.
If your silicon is -2 or -3 you might try to use the QPLL for a 5G rate. However you should repeat the SRIO characterization in PVT if you change the GTX PLL in your SRIO design.
My personal opinion is to try to fix the reasons why the 5G SRIO fails on your board. I would start by checking the REFCLK phase noise, power noise, layout and signal integrity. IBERT could represent an ideal situation: in the final design the FPGA real workload is higher and could for example increase the power noise, or some crosstalk could be present.
GT_DEBUGGER (XAPP1322 and XAPP1295) might help you in measuring the signal quality while working with SRIO.