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Registered: ‎04-12-2019

"tx/rx_core_clk" for JESD204C

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Hello,

https://www.xilinx.com/support/documentation/ip_documentation/jesd204c/v3_0/pg242-jesd204c.pdf

Above link says core clock can be provided by MGTREFCLK using "BUFG_GT" shown in Figure 3-3 of page 35.

I got an error saying O pin of IBUFD_GTE4 shown as below. But It was ok with ODIV2. Below is an example. I have to use the same frequency of core clock as MGTREFCLK.

IBUFDS_GTE4 Inst_ibufdsgt_if0_phyq0
( .CEB (1'b0),
.I (mgtrefclk0_x0y1_p),
.IB (mgtrefclk0_x0y1_n),

.O (if0_phyq0_refclk_1),
.ODIV2 (if0_phyq0_refclk_1_div2)
);

BUFG_GT m0Buf
( .I ( if0_phyq0_refclk_1),
//( .I ( if0_phyq0_refclk_1_div2),
.O ( if0_phyq0_refclk_1_core),
.CE ( gt_powergood_ce),
.DIV ( 3'b000),
.CLR ( 1'b0),
.CLRMASK ( 1'b0),
.CEMASK ( 1'b0)
);

Do you have any comment on this?

Thanks,

KW

CoreClk_BUFG_GT.PNG
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Registered: ‎08-01-2017

Re: "tx/rx_core_clk" for JESD204C

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As it says, the output of an IBUFDS_GTE can't drive a global buffer, because accordding to ug576 it has a dedicated routing straight to the GT core (its refclks). 

I saw the document and I guess it meant to use the odiv2 port of the buffer.

For your application there are 2 options:

1. Use the frequency of refclk for running core logic. You need to use the odiv2 output of the IBUFDS_GTE. In this way frequency of the clock you are getting could be the same refclk or its half with selecting the REFCLK_HROW_CK_SEL attribute. For more information please see page26 of ug576 section "Reference Clock Input/Output Structure".

2. Another way to use the clock from the GT core is to get the clock from GT's TXOUTCLK/RXOUTCLK. These clock are synced with TX refclk and recovered clock respectively. To do so, just insert a BUFG_GT at the output of one based on your application.


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Adventurer
Adventurer
277 Views
Registered: ‎08-01-2017

Re: "tx/rx_core_clk" for JESD204C

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As it says, the output of an IBUFDS_GTE can't drive a global buffer, because accordding to ug576 it has a dedicated routing straight to the GT core (its refclks). 

I saw the document and I guess it meant to use the odiv2 port of the buffer.

For your application there are 2 options:

1. Use the frequency of refclk for running core logic. You need to use the odiv2 output of the IBUFDS_GTE. In this way frequency of the clock you are getting could be the same refclk or its half with selecting the REFCLK_HROW_CK_SEL attribute. For more information please see page26 of ug576 section "Reference Clock Input/Output Structure".

2. Another way to use the clock from the GT core is to get the clock from GT's TXOUTCLK/RXOUTCLK. These clock are synced with TX refclk and recovered clock respectively. To do so, just insert a BUFG_GT at the output of one based on your application.


--
If this post was helpful, don't forget to give kudos, reply and accept as solution.

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Registered: ‎04-12-2019

Re: "tx/rx_core_clk" for JESD204C

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Hi,

Thanks for your comment. I'd rather use one of your option below.

.REFCLK_HROW_CK_SEL (2'b00), // 2'b00: ODIV2 = O

 

I am already using TXOUTCLK/RXOUTCLK for BRAM read/write clock for UltraScale+.

I am just wondering if there should be any specific configuration sequence for JESD204C & GTY block in case I choose TXOUTCLK/RXOUTCLK for "tx/rx_core_clk"? As TXOUTCLK/RXOUTCLK is output from GTY block..

Thanks,

KW

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