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mikerez
Explorer
Explorer
643 Views
Registered: ‎05-03-2012

rule output INT_DIVP is not set in 'rule "RXCDR_SETTINGS" {INT_RXCDR_TYPE INT_RX_OUTDIV USER_INS_LOSS_NYQ USER_PCIE_ENABLE USER_RX_

the message is from gtwizard_ultrascale:1.7

absolutely ununderstandable

please help to decode this

 

[xilinx.com:ip:gtwizard_ultrascale:1.7-1000] gtwizard_ultrascale_0: rule output INT_DIVP is not set in 'rule "RXCDR_SETTINGS" {INT_RXCDR_TYPE INT_RX_OUTDIV USER_INS_LOSS_NYQ USER_PCIE_ENABLE USER_RX_DATA_DECODING USER_RX_INT_DATA_WIDTH USER_RX_LINE_RATE USER_RX_PPM_OFFSET USER_RX_SSC_PPM} {INT_DIVF INT_DIVP INT_ENF INT_ENP INT_INCP INT_INCX INT_INCY}' at line 3124

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2 Replies
eschidl
Xilinx Employee
Xilinx Employee
569 Views
Registered: ‎10-19-2011

hi @mikerez ,

is this already happening with the example design of the transceiver core?

If yes, can you pass on the xci?

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mvisser
Observer
Observer
225 Views
Registered: ‎11-06-2018

I've run into this problem as well.

What I found was when I re-opened the wizard, the clock settings had been changed. I think what happened in my case was I changed the frequency of the free-running clock on page 2 of the wizard, and then the reference clock settings on the first page got changed to incorrect values. Updating the wizard and ensuring that all the settings are correct on all the pages fixed the issue.

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