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Observer
Observer
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Registered: ‎09-03-2018

two UltraScale FPGA transceivers IP clock unrout problem

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Hi, I use two UltraScale FPGA transceivers IP conneceted same reference clock, but it may have unrouted error

My reference clock is MGT222, pin assign at AT10 , AT9

Then my two IP RXP, RXN, TXP, TXN pin assign at  AV2, AV1, AV6, AV5 and AU4, AU3, AU8, AU7

Is there some rule make rout fail?

p.s. IP_1 use qpll0, IP_2 use qpll1

Thx

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Moderator
Moderator
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Registered: ‎07-30-2007

If you have an error message please include it.  It is hard to tell the problem for sure from the description but what is often the problem in this scenario is that each of the IP's will define an IBUFDS_GTE* and try to place it in the same spot.  You normally have to remove the IBUFDS_GTE* from one of the IP's and drive the signals it was driving from the the other IP.  In most IP's the IBUFDS_GTE* will be in the top level so it shouldn't be too tedious to make the change.  In some IP's you will need to make sure the buffer gets placed in the example design so that you have access to it.




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Moderator
Moderator
436 Views
Registered: ‎07-30-2007

If you have an error message please include it.  It is hard to tell the problem for sure from the description but what is often the problem in this scenario is that each of the IP's will define an IBUFDS_GTE* and try to place it in the same spot.  You normally have to remove the IBUFDS_GTE* from one of the IP's and drive the signals it was driving from the the other IP.  In most IP's the IBUFDS_GTE* will be in the top level so it shouldn't be too tedious to make the change.  In some IP's you will need to make sure the buffer gets placed in the example design so that you have access to it.




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