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Observer
Observer
461 Views
Registered: ‎09-03-2018

ultrascale fpga transceivers wizard cdr setting with 100FX module

Hi,I have asked a question about  ultrascale fpga transceivers wizard cdr setting,

the solution is  Set RXCDRHOLD = 1'b1 and RXCDROVRDEN = 1'b0.

Then if it possible I use a ultrascale fpga transceivers 1.25GHz to recieve or transmit 100-FX signal(100Mhz) when there is digital function to fix cdr issue .

Thanks

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Xilinx Employee
Xilinx Employee
373 Views
Registered: ‎03-30-2016

Hello @wuperry0125 

My understanding is , what  @iguo  was suggested is a setting to make your RX CDR lock to reference clock.
https://forums.xilinx.com/t5/FPGA-Configuration/ultrascale-fpga-transceivers-wizard-cdr-setting/m-p/1037287

As you may already aware that UltraScale GTH/GTY can only support minimum of 500Mbps.
To receive 100MHz (100Mbps) signal manually with UltraScale GTH/GTY, you need to implement oversampling the input signal by user logic.

As an alternative, If you want to receive 100BASE Ethernet
I would suggest to check PG047 below. Please check if this IP can fit your system. (External PHY is required though )
https://www.xilinx.com/support/documentation/ip_documentation/gig_ethernet_pcs_pma/v16_1/pg047-gig-eth-pcs-pma.pdf

Thanks & regards
Leo

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Observer
Observer
314 Views
Registered: ‎09-03-2018

So if I need to open cdr

I need to Set RXCDRHOLD = 1'b0 and RXCDROVRDEN = 1'b1 ?

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Xilinx Employee
Xilinx Employee
247 Views
Registered: ‎06-01-2017

For normal CDR operation, set RXCDRHOLD = 0 and RXCDROVRDEN = 0, which are the defaults when wizard is generated.
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